Register Set
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
19
Omni
ision
0E
COMF
01
RW
Common Control F
Bit[7]:
System clock selection
0:
Use 24 MHz system clock
1:
Use 48 MHz system clock
Bit[6:3]:
Reserved
Bit[2]:
Port output range selection
0:
Output data range is [001] to [3FE]
1:
Output data range is [000] to [3FF]
Bit[1]:
Reserved
Bit[0]:
AEC option
0:
Disable this function
1:
Enable larger AEC step increase with correct
exposure time
0F
COMG
47
RW
Common Control G
Bit[7]:
Optical black output selection
0:
Disable
1:
Enable
Bit[6]:
Black level calibrate selection
0:
Use electrical black reference
1:
Use optical black pixels to calibrate
Bit[5:4]:
Reserved
Bit[3]:
Channel offset adjustment
0:
Disable offset adjustment
1:
Enable offset adjustment, B/Gb/Gr/R channel offset
levels stored in registers RBIAS (see “BBIAS” on
page 24), GbBIAS (see “GbBIAS” on page 24),
GrBIAS (see “GrBIAS” on page 24) and RBIAS (see
“RBIAS” on page 25).
Bit[2]:
Data range selection
0:
Data range limited to [010] to [3F0]
1:
Full range
Bit[1]:
ADC black level calibration bias selection
0:
040
1:
010
Bit[0]:
ADC black level calibration enable
0:
Disable
1:
Enable
10
AEC
43
RW
Automatic Exposure Control Most Significant 8 bits for AEC[10:3] (least
significant 3 bits, AEC[2:0], in register COMB[2:0] - see “COMB” on
page 17).
AEC[10:0]:
Exposure time
TEX = tLINE x AEC[10:0]
Set COMI[2] = 0 (see “COMI” on page 21) to disable the AEC.
Table 11
Device Control Register List
Address
(Hex)
Register
Name
Default
(Hex)
R/W
Description
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