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OV9121 Datasheet(PDF) 24 Page - List of Unclassifed Manufacturers

Part # OV9121
Description  OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP
PDF  30 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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OV9121 Datasheet(HTML) 24 Page - List of Unclassifed Manufacturers

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Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
OV9625/OV9121
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
23
ROFF
EF
RW
R Channel Offset Adjustment - auto controlled by internal circuit if
COMG[0] = 1 (see “COMG” on page 19)
Bit[7]:
Offset direction
0:
Add ROFF[6:0]
1:
Subtract ROFF[6:0]
Bit[6:0]:
R channel offset adjustment value
24
AEW
A0
RW
Luminance Signal High Range for AEC/AGC Operation
AEC/AGC values will decrease in auto mode when average
luminance is greater than AEW[7:0]
25
AEB
88
RW
Luminance Signal Low Range for AEC/AGC Operation
AEC/AGC values will increase in auto mode when average
luminance is less than AEB[7:0].
26
VV
F4
RW
Fast Mode Large Step Range Thresholds - effective only in AEC/AGC
fast mode (COMI[7] = 1, see “COMI” on page 21)
Bit[7:4]:
High threshold
Bit[3:0]:
Low threshold
AEC/AGC may change in larger steps when luminance average is
greater than VV[7:4] or less than VV[3:0].
27
BBIAS
80
RW
B Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
Bit[7]:
Offset direction
0:
Add BBIAS[6:0]
1:
Subtract BBIAS[6:0]
Bit[6:0]:
B channel offset adjustment value
28
GbBIAS
80
RW
Gb Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
Bit[7]:
Offset direction
0:
Add GbBIAS[6:0]
1:
Subtract GbBIAS[6:0]
Bit[6:0]:
Gb channel offset adjustment value
29
GrBIAS
80
RW
Gr Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
Bit[7]:
Offset direction
0:
Add GrBIAS[6:0]
1:
Subtract GrBIAS[6:0]
Bit[6:0]:
Gr channel offset adjustment value
2A
COML
00
RW
Common Control L
Bit[7]:
Line interval adjustment. Interval adjustment value is in
COML[6:5] and FRARL[7:0] (see “FRARL” on page 25).
0:
Disabled
1:
Enabled
Bit[6:5]:
Line interval adjust value MSB 2 bits
Bit[4]:
Reserved
Bit[3:2]:
HSYNC timing end point adjustment MSB 2 bits
Bit[1:0]:
HSYNC timing start point adjustment MSB 2 bits
Table 11
Device Control Register List
Address
(Hex)
Register
Name
Default
(Hex)
R/W
Description



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