Register Set
Version 1.3, September 15, 2003
Proprietary to OmniVision Technologies
25
Omni
ision
2B
FRARL
00
RW
Line Interval Adjustment Value LSB 8 bits
The frame rate will be adjusted by changing the line interval. Each LSB
will add 2/1520 Tframe in SXGA and 2/800 Tframe in VGA mode to the
frame period.
2C
RBIAS
80
RW
R Channel Offset Manual Adjustment Value - effective only when
COMG[3] = 1 (see “COMG” on page 19).
Bit[7]:
Offset direction
0:
Add RBIAS[6:0]
1:
Subtract RBIAS[6:0]
Bit[6:0]:
R channel offset adjustment value
2D
ADDVSL
00
RW
VSYNC Pulse Width LSB 8 bits
Bit[7:0]:
Line periods added to VSYNC width. Default VSYNC
output width is 4 x tline. Each LSB count will add 1 x tline
to the VSYNC active period.
2E
ADDVSH
00
RW
VSYNC Pulse width MSB 8 bits
Bit[7:0]:
Line periods added to VSYNC width. Default VSYNC
output width is 4 x tline. Each MSB count will add
256 x tline to the VSYNC active period.
2F
YAVG
00
RW
Luminance Average
This register will auto update when COMH[5] = 1 (see “COMH” on
page 20). Average Luminance is calculated from the B/Gb/Gr/R
channel average as follows:
(BAVG[7:0] + GbAVG[7:0] + GrAVG[7:0] +RAVG[7:0])/4
30
HSDY
08
RW
HSYNC Position and Width Start Point Lower 8 bits
This register and COML[1:0] (see “COML” on page 24) define the
HSYNC start position, each LSB will shift HSYNC start point by 1 pixel
period.
31
HEDY
30
RW
HSYNC Position and Width End Point Lower 8 bits
This register and COML[3:2] (see “COML” on page 24) define the
HSYNC start position, each LSB will shift HSYNC start point by 1 pixel
period.
Table 11
Device Control Register List
Address
(Hex)
Register
Name
Default
(Hex)
R/W
Description
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