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M263 Datasheet(PDF) 273 Page - Nuvoton Technology Corporation

Part # M263
Description  Arm짰 Cortex짰-M 32-bit Microcontroller
PDF  398 Pages
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Manufacturer  NUVOTON [Nuvoton Technology Corporation]
Direct Link  http://www.nuvoton.com
Logo NUVOTON - Nuvoton Technology Corporation

M263 Datasheet(HTML) 273 Page - Nuvoton Technology Corporation

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M261/M262/M263
Mar 25, 2020
Page 273 of 398
Rev 1.02
AVDD
VBODL
BODOUT
BODRSTEN
Brown-out
Reset
T1
(< BODDGSEL)
T2
(= BODDGSEL)
T3
(= BODDGSEL)
Hysteresis
VBODH
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5
Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used
to check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog
time-out. User may decide to enable system reset during watchdog time-out to recover the system and
take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6
CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
unrecoverable exception
following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.2.2.7
CPU Reset, CHIP Reset and System Reset
The CPU Reset means only Cortex
® -M23 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset
signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
The System Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or



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