PFS123 datasheet(64/104 Pages) PADAUK

64 / 104 page

PFS123

8bit MTP MCU with 12-bit R-Type ADC

Page 64 of 104

PDK-DS-PFS123-EN_V000-Aug. 26, 2020

(7) Read the ADC result registers

5.15.1 The input requirement for AD conversion

For the AD conversion to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed

to fully charge to the voltage reference high level and discharge to the voltage reference low level. The

analog input model is shown as Fig.23, the signal driving source impedance (Rs) and the internal sampling

switch impedance (Rss) will affect the required time to charge the capacitor CHOLD directly. The internal

sampling switch impedance may vary with ADC supply voltage; the signal driving source impedance will

affect accuracy of analog input signal.

User must ensure the measured signal is stable before sampling;

therefore, the maximum signal driving source impedance is highly dependent on the frequency of signal to

be measured. The recommended maximum impedance for analog driving source is about 10KΩ under

500KHz input frequency.

Fig. 23: Analog Input Model

5.15.2 Select the reference high voltage

The ADC reference high voltage can be selected via bit[7] of register adcrgc and its option can be VDD or

PB1 from external pin.

5.15.3 ADC clock selection

Before starting the AD conversion, the minimum signal acquisition time should be met for the selected

analog input signal, the selection of ADCLK must be met the minimum signal acquisition time.

The clock of ADC module (ADCLK) can be selected by adcm register; there are 8 possible options for

ADCLK from CLK÷1 to CLK÷128 (CLK is the system clock). Due to the signal acquisition time TACQ is one

clock period of ADCLK, the ADCLK must meet that requirement. The recommended ADC clock is to

operate at 2us.

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