PFS123 datasheet(79/104 Pages) PADAUK

79 / 104 page

PFS123

8bit MTP MCU with 12-bit R-Type ADC

Page 79 of 104

PDK-DS-PFS123-EN_V000-Aug. 26, 2020

6.40. PWMG Clock Register (pwmgclk), IO address = 0x41

Bit

Reset

R/W

Description

PWMG Disable/ Enable

0: PWMG Disable

1: PWMG Enable

6 - 4

000

PWMG clock pre-scalar.

000: ÷1

001: ÷2

010: ÷4

011: ÷8

100: ÷16

101: ÷32

110: ÷64

111: ÷128

3 - 1

Reserved.

PWMG clock source selection

0: System Clock

1: IHRC or IHRC*2 (by code option PWM_Source)

6.41. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x42

Bit

Reset

R/W

Description

7 - 0

Bit[10:3] of PWMG0 Duty.

6.42. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x43

Bit

Reset

R/W

Description

7 - 5

Bit[2:0] of PWMG0 Duty.

4 - 0

Reserved.

Note: It’s necessary to write PWMG0 Duty_Value Low Register before writing PWMG0 Duty_Value High Register.

6.43. PWMG Counter Upper Bound High Register (pwmgcubh ), IO address = 0x44

Bit

Reset

R/W

Description

7 - 0

Bit[10:3] of PWMG Counter Bound.

6.44. PWMG Counter Upper Bound Low Register (pwmgcubl ), IO address = 0x45

Bit

Reset

R/W

Description

7 - 6

Bit[2:1] of PWMG Counter Bound.

5 - 0

Reserved.

PFS123 Datasheet(PDF) 79 Page - PADAUK Technology.

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