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PFS123 Datasheet(PDF) 36 Page - PADAUK Technology. |
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PFS123 Datasheet(HTML) 36 Page - PADAUK Technology. |
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36 / 104 page  PFS123 8bit MTP MCU with 12-bit R-Type ADC ©Copyright 2020, PADAUK Technology Co. Ltd Page 36 of 104 PDK-DS-PFS123-EN_V000-Aug. 26, 2020 5.4.5. System Clock and LVR level The clock source of system clock comes from EOSC, IHRC and ILRC, the hardware diagram of system clock in the PFS123 is shown as Fig.3. Fig.3: Options of System Clock User can choose different operating system clock depends on its requirement; the selected operating system clock should be combined with supply voltage and LVR level to make system stable. The LVR level will be selected during compilation, and the lowest LVR levels can be chosen for different operating frequencies. Please refer to Section 4.1. M U X clkmd[7:5] System clock CLK ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 ÷1, ÷4, ÷16 ÷1, ÷2, ÷4, ÷8 IHRC EOSC ILRC |
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