PFS123 datasheet(71/104 Pages) PADAUK

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PFS123

8bit MTP MCU with 12-bit R-Type ADC

Page 71 of 104

PDK-DS-PFS123-EN_V000-Aug. 26, 2020

6.10.Port B Digital Input Enable Register (pbdier), IO address = 0x0e

Bit

Reset

R/W

Description

7 - 6

Enable PB7~PB6 digital input and wake-up event.

1 / 0 : enable / disable

These bits can be set to low to prevent leakage current when PB7~PB6 are assigned as AD

inputs. When disable is selected, the wake-up function from these pins are also disabled.

Enable PB5 digital input, wake-up event and interrupt request.

1 / 0 : enable / disable

This bit should be set to low when PB5 is assigned as AD input to prevent leakage current. If

this bit is set to low, PB5 can NOT be used to wake-up the system and interrupt request from

this pin.

4 - 1

1111

Enable PB4~PB1 digital input and wake-up event.

1 / 0 : enable / disable

These bits can be set to low to prevent leakage current when PB4~PB1 are assigned as AD

inputs. When disable is selected, the wake-up function from these pins are also disabled.

Enable PB0 digital input, wake-up event and interrupt request.

1 / 0 : enable / disable

This bit should be set to low when PB0 is assigned as AD input to prevent leakage current. If

this bit is set to low, PB0 can NOT be used to wake-up the system and interrupt request from

this pin.

6.11.Port C Digital Input Enable Register (pcdier), IO address = 0x0f

Bit

Reset

R/W

Description

7 - 4

Reserved.

3 - 0

0xF

Enable PC3~PC0 digital input and wake-up event.

1 / 0 : enable / disable

These bits can be set to low to prevent leakage current when PC2~PC1 are assigned as AD

inputs. When disable is selected, the wake-up function and interrupt requests from these

pins are also disabled.

Note: Detail settings please refer to Section 9.3.

6.12. Port A Data Register (pa), IO address = 0x10

Bit

Reset

R/W

Description

7 - 0

0x00

R/W

Data register for Port A.

6.13. Port A Control Register (pac), IO address = 0x11

Bit

Reset

R/W

Description

7 - 0

0x00

R/W

Port A control registers. This register is used to define input mode or output mode for each

corresponding pin of port A.

0 / 1: input / output

Please note that PA5 can be INPUT or OUTPUT LOW ONLY, the output state will be tri-state

when PA5 is programmed into output mode with data 1.

PFS123 Datasheet(PDF) 71 Page - PADAUK Technology.

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