PFS172 datasheet(58/92 Pages) PADAUK

58 / 92 page

PFS172

8bit MTP MCU with 8-bit ADC

Page 58 of 92

PDK-DS-PFS172-EN_V000-May 8, 2020

There are 5 registers when using the ADC module, which are:

 ADC Control Register (adcc)

 ADC Mode Register (adcm)

 ADC Result Register (adcr)

 Port A/B Digital Input Enable Register (padier, pbdier)

The following steps are required to do the AD conversion procedure:

(1) Configure the AD conversion clock by adcm register

(2) Configure the pin as analog input by padier, pbdier register

(3) Select the ADC input channel by adcc register

(4) Enable the ADC module by adcc register

(5) Execute the AD conversion and check if ADC data is ready

set ‘1’ to addc.6 to start the conversion and check whether addc.6 is ‘1’

(6) Read the ADC result registers

5.13.1 The input requirement for AD conversion

For the AD conversion to meet its specified accuracy, the charge holding capacitor (CHOLD) must be

allowed to fully charge to the voltage reference high level and discharge to the voltage reference low level.

The analog input model is shown as Fig.19, the signal driving source impedance (Rs) and the internal

sampling switch impedance (Rss) will affect the required time to charge the capacitor CHOLD directly. The

internal sampling switch impedance may vary with ADC supply voltage; the signal driving source

impedance will affect accuracy of analog input signal.

User must ensure the measured signal is stable

before sampling; therefore, the maximum signal driving source impedance is highly dependent on the

frequency of signal to be measured. The recommended maximum impedance for analog driving source is

about 10KΩ under 500KHz input frequency.

Fig.19: Analog Input Model

Before starting the AD conversion, the minimum signal acquisition time should be met for the selected

analog input signal, the selection of ADCLK must be met the minimum signal acquisition time.

PFS172 Datasheet(PDF) 58 Page - PADAUK Technology.