PFS172 datasheet(62/92 Pages) PADAUK

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PFS172

8bit MTP MCU with 8-bit ADC

Page 62 of 92

PDK-DS-PFS172-EN_V000-May 8, 2020

6.6. Timer16 mode Register (t16m), IO address = 0x06

Bit

Reset

R/W

Description

7 - 5

000

R/W

Timer16 Clock source selection.

000: disable

001: CLK (system clock)

010: reserved

011: PA4 falling edge (from external pin)

100: IHRC

101: EOSC

110: ILRC

111: PA0 falling edge (from external pin)

4 - 3

R/W

Timer16 clock pre-divider.

00: ÷1

01: ÷4

10: ÷16

11: ÷64

2 - 0

000

R/W

Interrupt source selection. Interrupt event happens when the selected bit status is changed.

0 : bit 8 of Timer16

1 : bit 9 of Timer16

2 : bit 10 of Timer16

3 : bit 11 of Timer16

4 : bit 12 of Timer16

5 : bit 13 of Timer16

6 : bit 14 of Timer16

7 : bit 15 of Timer16

6.7. External Oscillator setting Register (eoscr), IO address = 0x0a

Bit

Reset

R/W

Description

Enable external crystal oscillator.

0 / 1 : Disable / Enable

6 - 5

External crystal oscillator selection.

00 : reserved

01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator

10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator

11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator

4 - 1

Reserved. Please keep 0 for future compatibility.

Power-down the Bandgap and LVR hardware modules. 0 / 1: normal / power-down.

PFS172 Datasheet(PDF) 62 Page - PADAUK Technology.

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