PFS172 datasheet(66/92 Pages) PADAUK

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PFS172

8bit MTP MCU with 8-bit ADC

Page 66 of 92

PDK-DS-PFS172-EN_V000-May 8, 2020

6.20. ADC Mode Register (adcm), IO address = 0x21

Bit

Reset

R/W

Description

7 - 4

Reserved. (keep 0 for future compatibility)

3 - 1

000

R/W

ADC clock source selection.

000: CLK (system clock) ÷ 1,

001: CLK (system clock) ÷ 2,

010: CLK (system clock) ÷ 4,

011: CLK (system clock) ÷ 8,

100: CLK (system clock) ÷ 16,

101: CLK (system clock) ÷ 32,

110: CLK (system clock) ÷ 64,

111: CLK (system clock) ÷ 128,

Reserved.

6.21. ADC Result Register (adcr), IO address = 0x22

Bit

Reset

R/W

Description

7 - 0

These eight read-only bits are the AD conversion result.

6.22. MISC Register (misc), IO address = 0x26

Bit

Reset

R/W

Description

7 - 6

Reserved. (keep 0 for future compatibility)

Enable fast Wake up. Fast wake-up is NOT supported when EOSC is enabled.

0: Normal wake up. The wake-up time is 3000 ILRC clocks (Not for fast boot-up)

1: Fast wake up. The wake-up time is 45 ILRC clocks.

Reserved.

Disable LVR function. 0 / 1 : Enable / Disable

1 - 0

Watch dog time out period

00: 8k ILRC clock period

01: 16k ILRC clock period

10: 64k ILRC clock period

11: 256k ILRC clock period

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