W6100 datasheet(132/149 Pages) WIZNET

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W6100 – Hardwired Dual TCP/IP Stack Controller

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6.8

Others Functions

6.8.1 System Clock(SYS_CLK) Switching

SYS_CLK operates in 25MHz or 100MHz and can be set by SYCR1[CLKSEL], PHYCR1[RST], or

PHYCR1[PWDN]. When clock switching happens, it take times until SYS_CLK becomes stable.

Refer to 6.7 Retransmission.

SYCR1[CLKSEL]

PHYCR1[RST]

PHYCR1[PWDN]

SYS_CLK(MHz)

100 (Default)

6.8.2 Ethernet PHY Operation Mode Configuration

PHY operation mode (Speed, Duplex) is set by PHYCR0 and it becomes valid after Ethernet PHY

HW reset. PHY operation mode can be checked with PHYSR[5:3] and link state with PHYSR[2:0]

after Ethernet PHY link up.

PHYCR0 can be configured only when PHYLCKR is unlocked.

Ex) Setting PHY Operation Mode

PHY_10FDX :

{

/* PHYCR0 & PHYCR1 Unlock */

PHYLCKR = 0x53;

/* Set PHYCR0 100/10BASE & Full/Duplex */

phy_mode = ‘000’

// Auto Negotiation

//phy_mode = ‘100’

// 100BASE-TX FDX

//phy_mode = ‘101’

// 100BASE-TX HDX

//phy_mode = ‘110’

// 10BASE-TX FDX

//phy_mode = ‘111’

// 10BASE-TX HDX

PHYCR0[2:0] = phy_mode;

/* PHY Reset Process */

PHYCR1[RST] = ‘1’;

Wait TPRST;

// refer to 8.4.1 Reset Timing

/* PHYCR0 & PHYCR1 Lock */

PHYLCKR = 0x00;

// for Lock, write any value

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