W6100 datasheet(136/149 Pages) WIZNET

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W6100 Datasheet(PDF) 136 Page - WIZnet Co., Ltd

Part #	W6100

Description	Hardwired Dual TCP/IP Stack Controller

PDF	149 Pages

Scroll/Zoom	100%

Manufacturer	WIZNET [WIZnet Co., Ltd]

Direct Link	https://www.wiznet.io/ko/Product/

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136 / 149 page

W6100 – Hardwired Dual TCP/IP Stack Controller

136/149

Data = 0x8000; /* set RST bit in BMCR */

PHYDIR1 = (Data & 0xFF00) >> 8; /* set upper 8bits Data */

PHYDIR0 = Data & 0x00FF;

/* set lower 8bits Data */

}

 Write Access / Complete?

If PHYACR is set to ‘0x01’, data in PHYDIR is written to PHY register, which is designated in

PHYRAR. PHYACR will be cleared automatically.

{

PHYACR = 0x01;

/* set Write Access */

while(PHYACR != 0); /* wait until MDC/MDIO Control is complete */

}

Figure 36 shows MDC/MDIO Read Control Flow.

Figure 36 MDC/MDIO Read Control Flow

 Config PHY Register Address

Stores the address of PHY register to access into PHYRAR.

{

START :

/* set PHY Register Address into PHYRAR */

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