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W6100 Datasheet(PDF) 137 Page - WIZnet Co., Ltd |
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W6100 Datasheet(HTML) 137 Page - WIZnet Co., Ltd |
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137 / 149 page  W6100 – Hardwired Dual TCP/IP Stack Controller 137/149 PHYRAR = 0x01; /* BMSR Address is 0x01 */ } Read Access / Complete? If PHYACR is set to ‘0x02’, data in PHY register, which is designated in PHYRAR, transfers to PHYDOR. PHYACR will be cleared automatically. { PHYACR = 0x02; /* set Read Access */ while(PHYACR != 0); /* wait until MDC/MDIO Control is complete */ } Read Output Data Data in PHY register is stored to PHYDOR0 & PHYDOR1. The most significant 8 bits in PHYDOR1 / the least significant 8 bits in PHYDOR0. { Data = (PHYDOR1 & 0x00FF) << 8; /* get upper 8bits Data */ Data = Data + (PHYDOR0 & 0x00FF); /* get lower 8bits Data */ } 6.8.7 Ethernet PHY 10BASE-Te Mode W6100 Ethernet PHY can operate in 10BASE-Te mode and below is the setting procedure. { /* PHYCR0&PHYCR1 Unlock */ PHYLCKR = 0x53; /* Enable Auto-negotiation */ PHYCR0[2:0] = ‘000’; /* set PHY Te Mode */ PHYCR1[TE] = ‘1’; /* PHY Reset Process */ PHYCR1[RST] = ‘1’; Wait TPRST; // refer to 8.4.1 Reset Timing } |
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