Data Sheet

AD4115

Rev. 0 | Page 49 of 51

Bits

Bit Name

Settings

Description

Reset

Access

[9:8]

INBUFx

Input buffer. This bit enables or disables input buffers.

0x0

R/W

00

Disabled.

01

Reserved.

10

Reserved.

11

Enabled.

[7:6]

Reserved

These bits are reserved. Set these bits to 0.

0x0

R

[5:4]

REF_SELx

These bits allow the user to select the reference source for ADC conversion on

Setup 0.

0x0

R/W

00

External reference, REF±.

10

Internal 2.5 V reference, must be enabled via ADCMODE (see Table 22).

11

AVDD − AVSS.

[3:0]

Reserved

These bits are reserved. Set these bits to 0.

0x0

R

FILTER CONFIGURATION REGISTER 0 TO FILTER CONFIGURATION REGISTER 7

Address: 0x28 to 0x2F, Reset: 0x0500, Name: FILTCON0 to FILTCON7

The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets

any active ADC conversion and restarts converting at the first channel in the sequence. The layout for FILTCON0 to FILTCON7 is identical.

Table 30. Bit Descriptions for FILTCON0 to FILTCON7

Bits

Bit Name

Settings

Description

Reset

Access

15

SINC3_MAPx

If this bit is set, the mapping of the filter register changes to directly

program the decimation rate of the sinc3 filter for Setup x. All other

options are eliminated. This bit allows fine tuning of the output data

rate and filter notch for rejection of specific frequencies. The data

0x0

R/W

[14:12]

Reserved

These bits are reserved. Set these bits to 0.

0x0

R

11

ENHFILTENx

This bit enables various postfilters for enhanced 50 Hz/60 Hz

rejection for Setup x. The ORDERx bits must be set to 00 to select the

sinc5 + sinc1 filter for this function to work.

0x0

R/W

0

Disabled.

1

Enabled.

[10:8]

ENHFILTx

These bits select between various postfilters for enhanced 50 Hz/

60 Hz rejection for Setup x.

0x5

R/W

010

27 SPS, 47 dB rejection, 36.7 ms settling.

011

25 SPS, 62 dB rejection, 40 ms settling.

101

20 SPS, 86 dB rejection, 50 ms settling.

110

16.67 SPS, 92 dB rejection, 60 ms settling.

7

Reserved

This bit is reserved. Set this bit to 0.

0x0

R

[6:5]

ORDERx

These bits control the order of the digital filter that processes the

modulator data for Setup x.

0x0

R/W

00

Sinc5 + sinc1 (default).

11

Sinc3.

[4:0]

ODRx

These bits control the output data rate of the ADC and, therefore, the

settling time and noise for Setup x. Rates shown are for a single-channel

enabled sinc5 + sinc 1 filter. See Table 16 for multiple channels

enabled.

0x0

R/W

00000

125,000 SPS.

00001

125,000 SPS.

00010

62,500 SPS.

00011

62,500 SPS.

00100

31,250 SPS.

00101

25,000 SPS.

00110

15,625 SPS.

00111

10,417 SPS.