AD4115 datasheet(9/51 Pages) AD

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Data Sheet

AD4115

Rev. 0 | Page 9 of 51

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VINCOM

VIN0

VIN1

VIN2

VIN3

REFOUT

REGCAPA

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT ANYTHING TO DNC.

DNC IS INTERNALLY CONNECTED TO AVSS.

2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON

THE PCB THAT IS UNDER THE EXPOSED PAD TO CONFER MECHANICAL

STRENGTH TO THE PACKAGE AND FOR HEAT DISSIPATION. THE EXPOSED

PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD ON THE PCB.

AVSS

AVDD

DNC

23 GPIO0

24 GPIO1

25 GPO2

26 VIN4

27 VIN5

28 VIN6

29 VIN7

30 VIN8

22 REGCAPD

21 DGND

TOP VIEW

(Not to Scale)

AD4115

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic1

Type2

Description

VINCOM

Voltage Input Common. Voltage inputs are referenced to VINCOM when the inputs are configured as

single-ended. Connect VINCOM to analog ground.

VIN0

Voltage Input 0. VIN0 is either referenced to VINCOM in single-ended configuration or referenced to a

positive input of an input pair with VIN1 in differential configuration.

VIN1

Voltage Input 1. VIN1 is either referenced to VINCOM in single-ended configuration or referenced to a

negative input of an input pair with VIN0 in differential configuration.

VIN2

Voltage Input 2. VIN2 is either referenced to VINCOM in single-ended configuration or referenced to a

positive input of an input pair with VIN3 in differential configuration.

VIN3

Voltage Input 3. VIN3 is either referenced to VINCOM in single-ended configuration or referenced to a

negative input of an input pair with VIN2 in differential configuration.

REFOUT

Internal Reference Buffered Output. The output is 2.5 V with respect to AVSS. Decouple REFOUT to AVSS

using a 0.1 µF capacitor.

REGCAPA

Analog Low Dropout (LDO) Regulator Output. Decouple REGCAPA to AVSS using a 1 µF capacitor and a

0.1 µF capacitor.

AVSS

Negative Analog Supply. AVSS ranges from −2.75 V to 0 V and is nominally set to 0 V.

AVDD

Analog Supply Voltage. AVDD ranges from 3.0 V to 5.5 V with respect to AVSS.

DNC

N/A

Do Not Connect. Do not connect anything to DNC. DNC is internally connected to AVSS.

VBIAS−

Voltage Bias Negative. VBIAS− sets the bias voltage for the voltage input AFE. Connect VBIAS− to AVSS.

XTAL1

Input 1 for Crystal.

XTAL2/CLKIO

AI/DI

Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADC Mode Register

section for more information.

DOUT/RDY

Serial Data Output/Data Ready Output. The DOUT/RDY dual-purpose pin functions as a serial data

output pin to access the output shift register on the ADC. The output shift register can contain data from

any on-chip data or control registers. The data-word or control word information is placed on the

DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the

DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a

data ready pin and goes low to indicate the completion of a conversion. If the data is not read after the

conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as

an interrupt to a processor that indicates that valid data is available.

DIN

Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to

the control registers on the ADC, and the register address (RA) bits of the communications register

identify the appropriate register. Data is clocked in on the rising edge of SCLK.

SCLK

Serial Clock Input. The SCLK serial clock input is used for data transfers to and from the ADC. SCLK has a

Schmitt triggered input.

Chip Select Input. CS is an active low logic input used to select the ADC. Use CS to select the ADC in

systems with more than one device on the serial bus. CS can be hardwired low to allow the ADC to

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