AD4115 datasheet(15/51 Pages) AD

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Data Sheet

AD4115

Rev. 0 | Page 15 of 51

POWER SUPPLIES

The AD4115 has two independent power supply pins, AVDD

and IOVDD. The AD4115 has no specific requirements for a

power supply sequence. However, when all power supplies are

stable, a device reset is required. See the AD4115 Reset section

for information on how to reset the device.

AVDD powers the internal 1.8 V analog LDO regulator that

powers the ADC core. AVDD also powers the crosspoint

multiplexer and integrated input buffers. AVDD is referenced to

AVSS, and AVDD − AVSS = 5 V. AVDD and AVSS can be a

single 5 V supply or ±2.5 V split supplies. Consider the absolute

maximum ratings when using split supplies (see the Absolute

Maximum Ratings section).

IOVDD powers the internal 1.8 V digital LDO regulator that

powers the ADC digital logic. IOVDD sets the voltage levels for

the serial peripheral interface (SPI) of the ADC. IOVDD is

referenced to DGND, and the voltage from IOVDD to DGND can

vary from 2 V (minimum) to 5.5 V (maximum).

Single-Supply Operation (AVSS = DGND)

When the AD4115 is powered from a single supply connected

to AVDD, the supply must be 5 V. In this configuration, AVSS

and DGND can be shorted together on a single ground plane.

IOVDD can range from 2 V to 5.5 V in this unipolar input

configuration.

DIGITAL COMMUNICATION

The AD4115 has either a 3-wire or 4-wire SPI interface that is

compatible with QSPI™, MICROWIRE®, and digital signal

processors (DSPs). The interface operates in SPI Mode 3 and can

be operated with CS tied low. In SPI Mode 3, SCLK idles high, the

falling edge of SCLK is the drive edge, and the rising edge of

SCLK is the sample edge. Data is clocked out on the falling

(drive) edge and data is clocked in on the rising (sample) edge.

DRIVE EDGE

SAMPLE EDGE

Figure 20. SPI Mode 3 SCLK Edges

Accessing the ADC Register Map

The communications register controls access to the full ADC

power-up or after a reset, the digital interface defaults to a state

where the interface expects a write to the communications

communications register.

The data written to the communications register determines

which register is accessed and if the next operation is a read or

write. The RA bits (Bits[5:0] in Register Address 0x00)

determine the specific register to which the read or write

operation applies (see Table 20).

When the read or write operation to the selected register is

complete, the interface returns to the default state to expect a

write operation to the communications register.

Figure 21 and Figure 22 show a write to and a read from a

Figure 21 shows an 8-bit command with the register address

followed by 8 bits, 16 bits, or 24 bits of data where the data

length on DIN depends on the selected register. Figure 22

shows an 8-bit command with the register address followed by

8 bits, 16 bits, 24 bits, or 32 bits of data where the data length

on DOUT depends on the selected register.

To verify correct communication with the device, read the ID

value of 0x38DX for the AD4115. The communication register

and ID register details are described in Table 7 and Table 8.

8-BIT COMMAND

8-BIT CRC

UP TO 24-BIT INPUT

CMD

DATA

CRC

DIN

SCLK

Figure 21. Writing to a Register

8-BIT COMMAND

8-BIT CRC

UP TO 32-BIT OUTPUT

CMD

DATA

CRC

DIN

SCLK

DOUT/

RDY

Figure 22. Reading from a Register

AD4115 RESET

When a power-up cycle completes and the power supplies are

stable, a device reset is required. If interface synchronization is

lost, a device reset is required. A write operation of at least 64 serial

clock cycles with DIN high returns the ADC to the default state

by resetting the entire device, including the register contents.

Alternatively, if CS is used with the digital interface, returning CS

high sets the digital interface to the default state and halts any

serial interface operation.

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