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Data Sheet

AD4115

Rev. 0 | Page 17 of 51

CONFIGURATION OVERVIEW

After a power-on or reset, the AD4115 default configuration is

as follows:

•

Channel configuration: Channel 0 is enabled, the VIN0

and VIN1 pair is selected as the input. Setup 0 is selected

(see the Setup Configuration section for more information).

•

Setup configuration: the analog input buffers and the

reference input buffers are disabled. The REF+ and REF− pins

are selected as the reference source. Note that for this setup,

the default channel does not operate correctly because the

input buffers must be enabled for a VINx input.

•

Filter configuration: the sinc5 + sinc1 filter is selected and

the maximum output data rate of 125 kSPS is selected.

•

ADC mode: continuous conversion mode and the internal

oscillator are enabled. The internal reference is disabled.

•

Interface mode: cyclic redundancy check (CRC) and the

data and status output are disabled.

Note that only a few of the register setting options are shown in

this example list. For full register information, see the Register

Details section.

Figure 23 shows an overview of the suggested flow for changing

the ADC configuration, divided into the following three blocks:

•

Channel configuration.

•

Setup configuration.

•

ADC mode and interface mode configuration.

Channel Configuration

The AD4115 has 16 independent channels and eight independent

setups. The user can select any input pair on any channel, as

well as any of the eight setups for any channel, which allows full

flexibility in the channel configuration. This flexibility allows per

channel configuration when using differential inputs and single-

ended inputs because each channel can have an individual

dedicated setup.

Channel Registers

The channel registers select which voltage input is used for the

corresponding channel. Each channel register contains a channel

enable/disable bit and the setup selection bits that select from

eight available setups to use for the channel.

When the AD4115 operates with more than one channel enabled,

the channel sequencer cycles through the enabled channels in

sequential order from Channel 0 to Channel 15. If a channel is

disabled, that channel is skipped by the sequencer. Details on

the channel register for Channel 0 are shown in Table 9.

ADC MODE AND INTERFACE MODE CONFIGURATION

SELECT ADC OPERATING MODE, CLOCK SOURCE,

ENABLE CRC, DATA AND STATUS, AND MORE

SETUP CONFIGURATION

8 POSSIBLE ADC SETUPS

SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE

CHANNEL CONFIGURATION

SELECT INPUT AND SETUP FOR EACH ADC CHANNEL

Figure 23. Suggested ADC Configuration Flow

Table 9. Channel Register 0 Bit Map

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

R/W

0x10

CH0

[15:8]

CH_EN0

SETUP_SEL0

Reserved

INPUT0[9:8]

0x8001

R/W

[7:0]

INPUT0[7:0]

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