AD4115 datasheet(23/51 Pages) AD

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Data Sheet

AD4115

Rev. 0 | Page 23 of 51

ABSOLUTE INPUT PIN VOLTAGES

The AD4115 voltage input pins are specified for an accuracy of

±10 V, specifically for the differential voltage between any two

voltage input pins.

The voltage input pins have separate specifications for the

absolute voltage that can be applied, and the unique design of

the voltage divider network of the analog front end enables

overvoltage robustness on the AD4115, which means the

allowed overvoltages vary depending on the AVDD supply.

Figure 26 shows the different degrees of robustness that can be

achieved for AVDD = 5 V. Figure 26 provides a visual

representation and guidance on how an overvoltage on a

voltage pin can affect the overall device accuracy.

The guaranteed accuracy section of Figure 26 shows the voltage

range that can be applied to a voltage input pin and achieve

guaranteed accuracy.

The no loss of accuracy sections show the voltage levels that can

be applied without degrading the accuracy of other channels.

The no damage to device sections show the allowable positive

and negative voltages that can be applied to a voltage input pin

without exceeding the absolute maximum. The performance of

other channels is degraded, but the performance recovers when

the overvoltage is removed. This voltage range is specified as an

absolute maximum rating of ±65 V.

Operation beyond the maximum operating conditions for

extended periods can affect product reliability.

ABSOLUTE MAXIMUM RATING

NO DAMAGE TO DEVICE

GUARANTEED ACCURACY

NO LOSS OF ACCURACY ON OTHER CHANNELS

+65V

–65V

–25V

–20V

+20V

+30V

AVDD = 5V

Figure 26. Absolute Input Pin Voltages, AVDD = 5 V

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage that results in a code of 00 … 00, a midscale voltage that

results in a code of 100 … 000, and a full-scale input voltage

that results in a code of 111 … 111.

The output code for any input voltage is represented with the

following equation:

Code = (2N × VIN × 0.1)/VREF

where:

N = 24 (the number of bits).

VIN is the input voltage.

VREF is the reference voltage.

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage that results in

a code of 000 … 000, a zero differential input voltage that results

in a code of 100 … 000, and a positive full-scale input voltage

that results in a code of 111 … 111. The output code for any

analog input voltage is represented with the following equation:

Code = 2N – 1 × ((VIN × 0.1/VREF) + 1)

AD4115 REFERENCE OPTIONS

The AD4115 provides the reference option of either supplying

an external reference to the REF+ and REF− device pins using

AVDD – AVSS as the reference, or allowing use of the internal

2.5 V, low noise, low drift reference. To select the reference

source to be used by the analog input, set the REF_SELx bits,

Bits[5:4], in the corresponding setup configuration register

appropriately. The structure of the Setup Configuration Register 0

is shown in Table 10. By default, the AD4115 uses an external

reference on power-up.

Internal Reference

The AD4115 includes a low noise, low drift, internal voltage

reference that has a 2.5 V output. The internal reference is

output on the REFOUT pin after the REF_EN bit in the ADC

mode register is set and is decoupled to AVSS with a 0.1 μF

capacitor. The AD4115 internal reference is disabled by default

on power-up.

External Reference

The AD4115 has a fully differential reference input applied

through the REF+ and REF− pins. Standard low noise, low drift

voltage references, such as the ADR4525, are recommended for

this use. Apply the external reference to the AD4115 reference

pins, as shown in Figure 27. Decouple the output of any external

reference to AVSS. As shown in Figure 27, the ADR4525 output

is decoupled with a 0.1 μF capacitor at the output for stability

purposes. The output is connected to a 4.7 μF capacitor that

acts as a reservoir for any dynamic charge required by the ADC

and is followed by another 0.1 μF decoupling capacitor at the

REF+ input. This capacitor is placed as close as possible to the

REF+ and REF− pins.

The REF− pin is connected directly to the AVSS potential. When

an external reference is used instead of the internal reference

to supply the AD4115, ensure that the REFOUT pin is not

hardwired to AVSS, which can draw a large current on power-

up. The internal reference is controlled by the REF_EN bit (Bit

15) in the ADC mode register, as shown in Table 14. If the

internal reference is not used elsewhere in the application,

ensure that the REF_EN bit is disabled.

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