AD4115 datasheet(6/51 Pages) AD

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AD4115

Data Sheet

Rev. 0 | Page 6 of 51

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

AVDD to AVSS

4.5

5.5

AVSS to DGND

−2.75

IOVDD to DGND

5.5

IOVDD to AVSS

For AVSS < DGND

6.35

POWER SUPPLY CURRENTS6

All outputs unloaded, digital inputs

connected to IOVDD or DGND

Full Operating Mode

AVDD Current

Including internal reference

9.4

11.5

IOVDD Current

Internal clock

1.4

1.8

Standby Mode

All VIN = 0 V

210

µA

Power-Down Mode

All VIN = 0 V

185

µA

POWER DISSIPATION

Full Operating Mode

Standby Mode

Power-Down Mode

925

µW

The full specification is guaranteed for a differential input signal of ±10 V. The device is functional up to a differential input signal of ±VREF × 10. However, the specified

absolute pin voltage must not be exceeded for the proper function.

Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected.

Specification is not production tested but is supported by characterization data at the initial product release.

This specification includes moisture sensitivity level (MSL) preconditioning effects.

VOUT is the output voltage.

This specification is with no load on the REFOUT pin and the digital output pins.

TIMING CHARACTERISTICS

IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, capacitive load (CLOAD) = 20 pF, unless otherwise noted.

Table 2.

Parameter1, 2

Limit at TMIN or TMAX

Unit

Test Conditions/Comments

SCLK

ns min

SCLK high pulse width

ns min

SCLK low pulse width

READ OPERATION

ns min

CS falling edge to DOUT/RDY active time

ns max

IOVDD = 4.75 V to 5.5 V

ns max

IOVDD = 2 V to 3.6 V

t23

ns min

SCLK active edge to data valid delay4

12.5

ns max

IOVDD = 4.75 V to 5.5 V

ns max

IOVDD = 2 V to 3.6 V

t55

2.5

ns min

Bus relinquish time after CS inactive edge

ns max

ns min

SCLK inactive edge to CS inactive edge

ns min

SCLK inactive edge to DOUT/RDY high/low

WRITE OPERATION

ns min

CS falling edge to SCLK active edge setup time4

ns min

Data valid to SCLK edge setup time

t10

ns min

Data valid to SCLK edge hold time

t11

ns min

CS rising edge to SCLK edge hold time

Sample tested during initial release to ensure compliance.

See Figure 2 and Figure 3.

This parameter is defined as the time required for the output to cross the VOL or VOH limit.

The SCLK active edge is the falling edge of SCLK.

DOUT/RDY returns high after a data register read. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while

DOUT/RDY is high. Ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read

only once.

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