Data Sheet

AD4682/AD4683

Rev. 0 | Page 5 of 30

TIMING SPECIFICATIONS

Figure 37, Figure 38, and Figure 39 for the timing diagrams. Multifunction pin names may be referenced by their relevant function only.

Table 3.

Parameter

Min

Typ

Max

Unit

Description

Time between conversions

1

µs

AD4682

2

µs

AD4683

190

ns

CS falling edge to first SCLK falling edge

25

ns

SCLK period

10

ns

SCLK high time

10

ns

SCLK low time

10

ns

CS pulse width

Interface quiet time prior to conversion

500

ns

AD4682

1500

ns

AD4683

CS low to SDOA and SDOB/ALERT enabled

6

ns

8

ns

3

ns

SCLK rising edge to SDOA and SDOB/ALERT hold time

SCLK rising edge to SDOA and SDOB/ALERT setup time

6

ns

8

ns

8

ns

CS rising edge to SDOA and SDOB/ALERT high impedance

1

ns

SDI setup time prior to SCLK falling edge

1

ns

SDI hold time after SCLK falling edge

0

ns

SCLK rising edge to CS rising edge

190

ns

Conversion time

ns

Acquire time

810

ns

AD4682

1810

ns

AD4683

Valid time to start conversion after software reset

250

ns

Valid time to start conversion after soft reset

800

ns

Valid time to start conversion after hard reset

Supply active to conversion

5

ms

First conversion allowed

11

ms

Settled to within 1% with internal reference

5

ms

Settled to within 1% with external reference

5

ms

Supply active to register read write access allowed

Exiting shutdown mode to conversion

11

ms

Settled to within 1% with internal reference

10

µs

Settled to within 1% with external reference

220

ns

Time from CS to ALERT indication

12

ns

Time from CS to ALERT clear