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AD4682/AD4683

Data Sheet

Rev. 0 | Page 18 of 30

MODES OF OPERATION

The AD4682 and the AD4683 have several on-chip configuration

registers for controlling the operational mode of the device.

Multifunction pin names may be referenced by their relevant

function only.

OVERSAMPLING

Oversampling is a common method used in analog electronics

to improve the accuracy of the ADC result. Multiple samples of

the analog input are captured and averaged to reduce the noise

component from the quantization noise and the thermal noise

(kTC) of the ADC. The AD4682 and the AD4683 offer an

oversampling function on chip, rolling average oversampling.

The rolling average oversampling functionality is enabled by

writing a 1 on the OS_MODE bit, Bit 9, and a valid nonzero

value on the OSR bits, Bits[8:6], in the CONFIGURATION1

OS_MODE bit, Bit 9, and a zero value on the OSR bits, Bits[8:6], of

the CONFIGURATION1 register.

Rolling Average Oversampling

Rolling average oversampling mode can be used in applications

where higher output data rates are required and where higher

SNR or dynamic range is required. Rolling average oversampling

involves taking a number of samples, adding the samples

together, and dividing the result by the number of samples

taken. This result is then output from the AD4682 or the

AD4683. The sample data is not cleared after the process

completes. The rolling average oversampling mode uses a first

in, first out (FIFO) buffer of the most recent samples in the

averaging calculation, allowing the ADC throughput rate and

output data rate to stay the same.

Rolling average oversampling mode is enabled by setting the

OS_MODE bit to Logic 1 and having a valid nonzero value in

the OSR bits. The oversampling ratio of the digital filter is

controlled using the oversampling bits, OSR (see Table 10). The

output result is decimated to 16-bit resolution for the AD4682 and

the AD4683. If additional resolution is required, configure the

resolution boost bit in the CONFIGURATION1 register. See

the Resolution Boost section for further details.

In rolling average oversampling mode, all ADC conversions are

controlled and initiated by the falling edge of CS. After a

conversion is complete, the result is loaded into the FIFO. The

FIFO length is 8, regardless of the oversampling ratio set. The

FIFO is filled on the first conversion after a power-on reset, the

first conversion after a software controlled hard or soft reset, or

the first conversion after the REFSEL bit is toggled. A new

conversion result is shifted into the FIFO on completion of

every ADC conversion, regardless of the status of the OSR bits

and the OS_MODE bit. This conversion allows a seamless

transition from no oversampling to rolling average oversampling

or different rolling average oversampling ratios without waiting

for the FIFO to fill.

The number of samples, n, defined by the OSR bits are taken

from the FIFO, added together, and the result is divided by n.

The time between CS falling edges is the cycle time, which can

be controlled by the user, depending on the required data

output rate.

RESOLUTION BOOST

The default conversion result output data size for the AD4682 and

the AD4683 is 16 bits. When the on-chip oversampling function is

enabled, the performance of the ADC can exceed the 16-bit level.

To accommodate the performance boost achievable, it is possible

to enable an additional two bits of resolution. If the RES bit in

the CONFIGURATION1 register is set to Logic 1, and the

AD4682 and the AD4683 are in a valid oversampling mode, the

conversion result size for the AD4682 and the AD4683 is 18 bits.

In this mode, 18 SCLKs are required to propagate the data.

Table 10. AD4682 Rolling Average Oversampling Performance Overview

OSR, Bits[8:6]

Oversampling Ratio

SNR (dB Typical)

Output Data Rate (kSPS Maximum)

VREF = 2.5 V

VREF = 3.3 V

RES = 0

RES = 1

RES = 0

RES = 1

000

Disabled

85.7

87.3

1000

001

87.6

87.9

88.8

89.3

1000

010

90.1

90.9

91.3

92.4

1000

011

92.6

94.0

93.4

95.4

1000

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