AD4682 datasheet(22/30 Pages) AD

22 / 30 page

AD4682/AD4683

Data Sheet

Rev. 0 | Page 22 of 30

Serial 2-Wire Mode

Configure 2-wire mode by setting the SDO bit in the

CONFIGURATION1 register to 0. In 2-wire mode, the conversion

result for ADC A is output on the SDOA pin, and the

conversion result for ADC B is output on the SDOB/ALERT pin

(see Figure 41).

Serial 1-Wire Mode

In applications where slower throughput rates are allowed, the

SPI can be configured to operate in 1-wire mode. In 1-wire mode,

the conversion results from ADC A and ADC B are output on

the serial output, SDOA. Additional SCLK cycles are required to

propagate all of the data. The ADC A data is output first,

followed by the ADC B conversion results (see Figure 42).

LOW LATENCY READBACK

The interface on the AD4682 and the AD4683 has a one cycle

latency, as shown in Figure 43. For applications that operate at

lower throughput rates, the latency of reading the conversion

result can be reduced. When the conversion time elapses, a

second CS pulse after the initial CS pulse that initiates the

conversion can readback the conversion result. This operation

is shown in Figure 43.

DON’T CARE

ADC A S0

ADC A S1

SDOA

SDOB

NOP

DON’T CARE

ADC B S0

ADC B S1

SDI

Figure 41. Reading Conversion Results: 2-Wire Mode

DON’T CARE

ADC A S1

ADC B S1

SDOA

NOP

ADC A S0

ADC B S0

SDI

Figure 42. Reading Conversion Results: 1-Wire Mode

DON'T CARE

ACQ

DON'T CARE

ACQ

INTERNAL

RESULTn

RESULTn + 1

CNVn + 1

CNVn

SDOA

SDOB

SCLK

TARGET SAMPLE PERIOD

Figure 43. Low Throughput Low Latency

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