AD4682 datasheet(14/30 Pages) AD

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AD4682/AD4683

Data Sheet

Rev. 0 | Page 14 of 30

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD4682 and the AD4683 are high speed, dual, simultaneous

sampling, pseudo differential, 16-bit, SAR ADCs. The AD4682

and the AD4683 operate from a 3.0 V to 3.6 V power supply and

feature throughput rates of 1 MSPS and 500 kSPS, respectively.

The AD4682 and the AD4682 contain two SAR ADCs and a

serial peripheral interface (SPI) with two separate data output

pins. The devices are housed in a 16-lead LFCSP, offering the

user considerable space-saving advantages over alternative

solutions.

Data is accessed from the devices via the SPI. The SPI can

operate with one or two serial outputs. The AD4682 and the

AD4682 have an on-chip 2.5 V internal reference, VREF. If an

external reference is required, disable the internal reference,

supply a reference value that ranges from 2.5 V to 3.3 V, and set

the REFSEL bit in the CONFIGURATION1 register to 1. If the

internal reference is used elsewhere in the system, buffer the

reference output. The pseudo differential analog input range

for the AD4682 and the AD4683 is the common-mode voltage

(VCM) ± VREF/2.

The AD4682 and the AD4683 feature an on-chip oversampling

block to improve performance. Rolling average oversampling

mode and power-down options that allow power saving between

conversions are also available. Configuration of the devices is

implemented via the standard SPI (see the Interface section).

CONVERTER OPERATION

The AD4682 and the AD4683 have two SAR ADCs, each based

around two capacitive digital-to-analog converters (DACs).

Figure 31 and Figure 32 show the simplified schematics of one

of these ADCs in acquisition and conversion phases, respectively.

The ADC comprises the control logic, an SAR, and two capacitive

DACs. In Figure 31 (the acquisition phase), SW3 is closed, SW1

and SW2 are in Position A, the comparator is held in a balanced

condition, and the sampling capacitor (CS) arrays can acquire

the pseudo differential signal on the input.

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VREF

CAPACITIVE

DAC

AINx+

AINx–

Figure 31. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 32), SW3 opens

and SW1 and SW2 move to Position B, causing the comparator

to become unbalanced. Both inputs are disconnected when the

conversion begins. The control logic and charge redistribution

DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator

back into a balanced condition. When the comparator is

rebalanced, the conversion completes. The control logic generates

the ADC output code. The output impedances of the sources

driving the AINx+ and AINx− pins must be matched. Otherwise,

the two inputs have different settling times, which results in errors.

COMPARATOR

SW1

SW2

VREF

CONTROL

LOGIC

SW3

CAPACITIVE

DAC

CAPACITIVE

DAC

AINx+

AINx–

Figure 32. ADC Conversion Phase

ANALOG INPUT STRUCTURE

Figure 33 shows the equivalent analog input circuit of the AD4682

and the AD4683. The four diodes (D) provide ESD protection

for the analog inputs. Ensure that the analog input signals do

not exceed the supply rails by more than 300 mV. Exceeding the

limit causes these diodes to become forward-biased and start

conducting into the substrate. These diodes can conduct up to

10 mA without causing irreversible damage to the devices.

The C1 capacitors in Figure 33 are typically 3 pF and can primarily

be attributed to pin capacitance. The R1 resistors are lumped

components made up of the on resistance of the switches. The

value of these resistors is typically about 200 Ω. The C2 capacitors

are sampling capacitors of the ADC with a capacitance of 15 pF

typically.

AINx+

VCC

AINx–

VCC

Figure 33. Equivalent Analog Input Circuit,

Conversion Phase—Switches Open, Track Phase—Switches Closed

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