AD4682 datasheet(19/30 Pages) AD

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Data Sheet

AD4682/AD4683

Rev. 0 | Page 19 of 30

ACQ

tCYC

ACQ

ENABLE OSR = 2

ENABLE OSR = 4

(f1+ f2)/2

DON’T CARE

SDOA

SDOB

SDI

VCC

INTERNAL

(f1 + f2)/2

(f1 + f2 + f3 + f4)/4

(f1 + f2)/2

FIFO

Figure 36. Rolling Average Oversampling Mode Configuration

SDOA

CONV

ACQ

CONV

ACQ

CONV

ACQ

CONV

ACQ

INTERNAL

ALERT

tALERTS

tALERTC

EXCEEDS THRESHOLD

NO OVERSAMPLING OR

ROLLING AVERAGE

OVERSAMPLING

Figure 37. Alert Operation

ALERT

The alert functionality is an out of range indicator and can be

used as an early indicator of an out of bounds conversion result.

An alert event triggers when the conversion result value register

exceeds the alert high limit value in the ALERT_HIGH_

THRESHOLD register or falls below the alert low limit value in

the ALERT_LOW_THRESHOLD register. The ALERT_HIGH_

THRESHOLD register and ALERT_LOW_THRESHOLD

limits, the alert high threshold must always be greater than the

alert low threshold. Detailed alert information is accessible in

the ALERT register.

The ALERT register contains two status bits per ADC, one

corresponding to the high limit, and the other to the low limit.

A logical OR of alert signals for all ADCs creates a common

alert value. This value can be configured to drive out on the

ALERT function of the SDOB/ALERT pin. The SDOB/ALERT pin

is configured as ALERT by configuring the following bits in the

CONFIGURATION1 and CONFIGURATION2 registers:

•

Set the SDO bit to 1.

•

Set the ALERT_EN bit to 1.

•

Set a valid value to the ALERT_HIGH_THRESHOLD

The alert indication function is available in rolling average

oversampling and nonoversampling modes.

The ALERT function of the SDOB/ALERT pin is updated at the

end of the conversion. The alert indication status bits in the

ALERT register are updated as well and must be read before the

end of the next conversion. The ALERT function of the

SDOB/ALERT pin is cleared with a falling edge of CS. Issuing a

software reset also clears the alert status in the ALERT register.

POWER MODES

The AD4682 and the AD4683 have two power modes, normal

and shutdown. These modes of operation provide flexible

power management options, allowing optimization of the

power dissipation and throughput rate ratio for different

application requirements.

Program the PMODE bit in the CONFIGURATION1 register

to configure the power modes in the AD4682 and the AD4683.

Set the PMODE bit to Logic 0 for normal mode and Logic 1 for

shutdown mode.

Normal Mode

Keep the AD4682 and the AD4683 in normal mode to achieve

the fastest throughput rate. All blocks within the AD4682 and

the AD4683 remain fully powered at all times, and an ADC

conversion can be initiated by a falling edge of CS, when required.

When the AD4682 and the AD4683 are not converting, the

devices are in static mode and power consumption is automatically

reduced. Additional current is required to perform a conversion.

Therefore, power consumption on the AD4682 and the AD4683

scales with throughput.

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