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AD4682 Datasheet(PDF) 8 Page - Analog Devices |
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AD4682 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 30 page ![]() AD4682/AD4683 Data Sheet Rev. 0 | Page 8 of 30 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 12 11 10 1 3 4 9 2 GND VLOGIC REGCAP VCC REFCAP GND CS REFIO NOTES 1. EXPOSED PAD. FOR PROPER OPERATION OF THE DEVICE, CONNECT THE EXPOSED PAD TO GROUND. AD4682/ AD4683 TOP VIEW (Not to Scale) Figure 6. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1, 10 GND Ground Reference Points. The GND pins are the ground reference points for all circuitry on the device. 2 VLOGIC Logic Interface Supply Voltage, 1.65 V to 3.6 V. Decouple VLOGIC to GND with a 1 µF capacitor. 3 REGCAP Decoupling Capacitor Pin for Voltage Output from the Internal Regulator. Decouple REGCAP to GND with a 1 µF capacitor. The voltage at REGCAP is 1.9 V typical. 4 VCC Power Supply Input Voltage, 3.0 V to 3.6 V. Decouple VCC to GND using a 1 µF capacitor. 5, 6 AINB−, AINB+ Analog Inputs of ADC B. The AINB− and AINB+ analog inputs form a pseudo differential pair. AINB− is typically connected to VREF/2, and the AINB+ voltage range is from 0 V to VREF. 7, 8 AINA−, AINA+ Analog Inputs of ADC A. The AINA− and AINA+ analog inputs form a pseudo differential pair. AINA− is typically connected to VREF/2, and the AINA+ voltage range is from 0 V to VREF. 9 REFCAP Decoupling Capacitor Pin for Band Gap Reference. Decouple REFCAP to GND with a 0.1 µF capacitor. The voltage at REFCAP is 2.5 V typical. 11 REFIO Reference Input and Output. The on-chip reference of 2.5 V is available as an output on REFIO for external use if the device is configured accordingly. Alternatively, an external reference of 2.5 V to 3.3 V can be input to REFIO. Set the REFSEL bit in the CONFIGURATION1 register to 1 when using the external reference, and apply the REFSEL bit after VCC and VLOGIC. Decoupling is required on REFIO for both the internal and external reference options. Apply a 1 µF capacitor from REFIO to GND. 12 CS Chip Select Input. Active low, logic input. CS provides the dual function of initiating conversions on the AD4682 and the AD4683 and framing the serial data transfer. 13 SDOA Serial Data Output A. SDOA functions as a serial data output pin to access the ADC A or ADC B conversion results or data from any of the on-chip registers. 14 SDOB/ALERT Serial Data Output B/Alert Indication Output. The SDOB/ALERT pin can operate as a serial data output pin or an alert indication output. SDOB functions as a serial data output pin to access the ADC B conversion results. ALERT operates as an alert pin going low to indicate that a conversion result exceeded a configured threshold. When using ALERT, set the SDO bit in the CONFIGURATION2 register to 1, and set the ALERT_EN bit to 1 in the CONFIGURATION1 register. 15 SDI Serial Data Input. SDI provides the data written to the on-chip control registers. 16 SCLK Serial Clock Input. SCLK is for data transfers to and from the ADC. EPAD Exposed Pad. For proper operation of the device, connect the exposed pad to ground. |
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