AD9083BBCZ datasheet(3/93 Pages) AD

3 / 93 page

Data Sheet

AD9083

Rev. 0 | Page 3 of 93

GENERAL DESCRIPTION

The AD9083 is a 16-channel, 125 MHz bandwidth, continuous

time Σ-Δ (CTSD) ADC. The device features an on-chip,

programmable, single-pole antialiasing filter and termination

resistor that is designed for low power, small size, and ease of

use.

The 16 ADC cores features a first-order, CTSD modulator

architecture with integrated, background nonlinearity

correction logic and self cancelling dither. Each ADC features

wide bandwidth inputs supporting a variety of user-selectable

input ranges. An integrated voltage reference eases design

considerations.

The analog input and clock signals are differential inputs. Each

ADC has a signal processing tile to filter out of band shaped

noise from the Σ-Δ ADC and reduce the sample rate. Each tile

contains a cascaded integrator comb (CIC) filter, a quadrature

digital downconverter (DDC) with multiple finite input

response (FIR) decimation filters (decimate by J block), or up

to three quadrature DDC channels with averaging decimation

filters for data gating applications.

Users can configure the Subclass 1 JESD204B based, high speed

serialized output in a variety of lane configurations (up to four),

depending on the DDC configuration and the acceptable lane rate

of the receiving logic device. Multiple device synchronization is

supported through the SYSREF±, TRIG±, and SYNCINB±

input pins.

The AD9083 has flexible power-down options that allow

significant power savings when desired. All of these features

can be programmed using a 1.8 V capable 3-wire serial port

interface (SPI).

The AD9083 is available in a Pb-free, 100-ball CSP_BGA and is

specified over the −40°C to +85°C industrial temperature range.

This product is protected by a U.S. patent.

AD9083BBCZ Datasheet(PDF) 3 Page - Analog Devices