AD9083BBCZ datasheet(83/93 Pages) AD

83 / 93 page

Data Sheet

AD9083

Rev. 0 | Page 83 of 93

Addr.

Name

Bits

Bit Name

Description

Reset Access

0x500 JTX_PLL_RST

[7:1]

RESERVED

Reserved.

0x0

RSTB_JTX_PLL_RC

Force link reset from REGMAP.

0x0

R/W

0x501 PLL_ENABLE_CTRL

PLL_LOCKED_BYPASS_VAL

Bypass value for PLL_LOCKED output when

PLL_LOCKED_BYPASS is 1. Select between PLL

lock signal and timer based lock signal

generation

0x0

R/W

PLL_LOCKED_BYPASS

Bypass control for PLL_LOCKED output.

0: use state machine value

1: use PLL_LOCKED_BYPASS_VAL). Select

between PLL lock signal and timer based lock

signal generation

0x0

R/W

JTX_PLL_BYPASS_LOCK

Bypass PLL lock input.

0x0

R/W

RESERVED

Reserved.

0x0

LOLSTICKYCLEAR_FORCE_

JTX_PLL_RC

Clears out loss of lock bit.

0x0

R/W

RESERVED

Reserved.

0x0

LDSYNTH_FORCE_JTX_PLL_A

to start calibration. A short "1" pulse starts VCO

calibration, the pulse width should be at least 1

reference clock period. Allows for user to do a

calibration at will.

0x0

R/W

PWRUP_JTX_PLL

Power up PLL. Power up PLL, starts LDO, Starts

Calibration, sends out PLL locked when done .

"Big green button", forces power up, will not

read back correctly if PLL is powered up

internally

0x0

R/W

0x502 PLL_STATUS

[7:5]

RESERVED

Reserved.

0x0

LOSSLOCK_JTX_PLL_RS

PLL went out-of-lock. Bit to indicate PLL went

out-of-lock at any time between frequency

acquisitions.

0x0

RFPLLLOCK_JTX_PLL_RS

PLL is locked when this bit is HIGH.

0x0

VCOCALINPROG_JTX_PLL_RS 0: when the last ALC is done (VCO cal. state

machine is in ALC_CAL_LSB state). 1: when

init_cal_redge=1 initiated by ld_synth

0x0

REGULATORRDY_JTX_PLL_RS High = indicates regulator voltage is above

threshold for at least cnt conversions

0x0

JTX_PLLLOCK_JTX_PLL_RS

PLL is locked when this bit is high.

0x0

0x506 PLL_ENCAL

[7:5]

RESERVED

Reserved.

0x0

PD_TXCLK_DIST_RC

txclk dist rc. Enable output clocks to serializer1 

SER

0x0

R/W

PD_RXCLK_DIST_RC

rxclk dist rc. Enable output clocks to serializer1 

SER

0x0

R/W

RESERVED

Reserved.

0x0

EN_TX_ONLY_JTX_PLL_RC

Enable output clocks to serializer

1  SER only

0x0

R/W

EN_OCTAVECAL_JTX_PLL_RC Determines whether to enable PLL octave

calibration.

0x0

R/W

0x507 JTX_PLL_REF_CLK_

DIV1_REG

REFCK_DIV40BDIV120_JTX_PLL Ref clock output (1/40 or 1/120).

0x0

R/W

DIVP_JTX_PLL_RC

Selects whether B is multiplied by 6 or 8. Selects

output division rate; 0->pd, 1->no divider, 2-

>divide by 2, 3->divide by 4

0x0

R/W

[5:4]

DIVM_JTX_PLL_RC

Selects output division rate;. Selects output

division rate; 0->/1, 1->/2. Bit [1] is not used.

0x2

R/W

RESERVED

Reserved.

0x0

[2:0]

REFINDIV_JTX_PLL_RC

Sets division rate on input:. Sets division rate on

input: 0->1, 1->2, 2->4, 3->8, 4 and above div 16

0x2

R/W

AD9083BBCZ Datasheet(PDF) 83 Page - Analog Devices

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