 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9083BBCZ Datasheet(PDF) 76 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9083BBCZ Datasheet(HTML) 76 Page - Analog Devices |
|
|
76 / 93 page  AD9083 Data Sheet Rev. 0 | Page 76 of 93 Addr. Name Bits Bit Name Description Reset Access 0x27B JTX_CORE_SYNC_N_ SEL [7:3] RESERVED Reserved. 0x0 R [2:0] JTX_SYNC_N_SEL Decimal value to select the physical sync_n source pin. Ignored when JTX_NUM_LINKS = 1. 0x0 R/W 0x27C JTX_CORE_13 [7:1] RESERVED Reserved. 0x0 R 0 JTX_LINK_EN See JTX documentation. 0x0 R/W 0x27D JTX_TPL_CONFIG0 [7:3] JTX_NS_CFG Number of unique samples per converter in conv_sample. 0x0 R/W 2 JTX_TPL_CONV_ ASYNCHRONOUS Expect link_pclk asynchronous to conv_clk. This will increase the delay for the domain handoff buffer in fixed latency mode. The increased delay may require setting the JTX_TPL_ASYNC_SUPPORT parameter. 0x0 R/W 1 JTX_TPL_TEST_ENABLE Enable long transport layer test. 0x0 R/W 0 JTX_TPL_ADAPTIVE_LATENCY Enable adaptive latency mode. Default should be 0. 0x0 R/W 0x27E JTX_TPL_CONFIG1 7 JTX_TPL_SYSREF_IGNORE_ WHEN_LINKED Mask incoming SYSREF when SYNC~ is de- asserted. Applies to 204B operation only. 0x0 R/W 6 JTX_TPL_SYSREF_CLR_ PHASE_ERR Clear jtx_tpl_SYSREF_phase_err. 0x0 R/W 5 JTX_TPL_SYSREF_MASK Mask any incoming SYSREF to 0. 0x0 R/W [4:3] RESERVED Reserved. 0x0 R 2 JTX_TPL_SYSREF_PHASE_ERR Incoming SYSREF has been registered at an unexpected time from the previously established SYSREF phase. 0x0 R 1 JTX_TPL_SYSREF_RCVD SYSREF phase has been established. 0x0 R 0 RESERVED Reserved 0x0 R 0x27F JTX_TPL_LATENCY_ ADJUST [7:0] JTX_TPL_LATENCY_ADJUST Add additional conv_clk cycles of latency (for both latency modes). Useful in adaptive latency mode to get a wider adaptable range. 0x0 R/W 0x280 JTX_TPL_PHASE_ ADJUST0 [7:0] JTX_TPL_PHASE_ADJUST[7:0] Output LMFC phase adjustment in conv_clk cycles. Maximum value is k*s/ns-1. 0x0 R/W 0x281 JTX_TPL_PHASE_ ADJUST1 [7:0] JTX_TPL_PHASE_ ADJUST[15:8] Output LMFC phase adjustment in conv_clk cycles. Maximum value is k*s/ns-1. 0x0 R/W 0x282 JTX_TPL_TEST_NUM_ FRAMES0 [7:0] JTX_TPL_TEST_NUM_ FRAMES_M1[7:0] Number of frames (minus 1) in the long transport layer test pattern. 0x0 R/W 0x283 JTX_TPL_TEST_NUM_ FRAMES1 [7:0] JTX_TPL_TEST_NUM_ FRAMES_M1[15:8] Number of frames (minus 1) in the long transport layer test pattern. 0x0 R/W 0x284 JTX_TPL_SYSREF_N_ SHOT [7:5] RESERVED Reserved. 0x0 R 4 JTX_TPL_SYSREF_N_SHOT_EN ABLE Mask all incoming SYSREF pulses except the Nth pulse specified by the n_shot_count. Disabling this will cause all SYSREF pulses to be sampled (continuous mode) and reset the n_shot counter. 0x0 R/W [3:0] JTX_TPL_SYSREF_N_SHOT_C OUNT Mask all incoming SYSREF pulses except the Nth pulse where N is the value programmed + 1. Only used when n_shot_enable is high. 0x0 R/W 0x285 JTX_TPL_BUF_FRAMES [7:0] JTX_TPL_BUF_FRAMES Frame delay through transport layer buffer. 0x0 R 0x286 JTX_L0_DID [7:0] JTX_DID_CFG Device (= link) identification no. 0x0 R/W 0x287 JTX_L0_ADJCNT_BID [7:4] JTX_ADJCNT_CFG Number of adjustment resolution steps to adjust DAC LMFC. Applies to Subclass 2 operation only. 0x0 R/W [3:0] JTX_BID_CFG Bank ID Extension to DID. 0x0 R/W [4:0] RESERVED Reserved. 0x0 R |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
