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AD9083BBCZ Datasheet(PDF) 15 Page - Analog Devices |
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AD9083BBCZ Datasheet(HTML) 15 Page - Analog Devices |
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15 / 93 page  Data Sheet AD9083 Rev. 0 | Page 15 of 93 Pin No. Mnemonic Type Description C6, C7, D7, E8, F8, G7, H5, H7, K10 AGND Ground Analog Ground. These AGND pins connect to the analog ground plane. E5 AGND Ground Ground Reference for AVDD. K4 AGND Ground Ground Reference for AVDD. D4, E4, F4, G4 DGND Ground Digital Ground. These DGND pins connect to the digital ground plane. A1, C1, C2, H2 DGND Ground Digital Driver Ground. These DGND pins connect to the digital driver ground plane. Analog A5, B5 VIN1+, VIN1− Input ADC 1 Analog Input True/Complement. A6, B6 VIN2+, VIN2− Input ADC 2 Analog Input True/Complement. A7, B7 VIN3+, VIN3− Input ADC 3 Analog Input True/Complement. A8, B8 VIN4+, VIN4− Input ADC 4 Analog Input True/Complement. A9, B9 VIN5+, VIN5− Input ADC 5 Analog Input True/Complement. C9, C10 VIN6−, VIN6+ Input ADC 6 Analog Input Complement/True. D9, D10 VIN7−, VIN7+ Input ADC 7 Analog Input Complement/True. E9, E10 VIN8−, VIN8+ Input ADC 8 Analog Input Complement/True. F9, F10 VIN9−, VIN9+ Input ADC 9 Analog Input Complement/True. G9, G10 VIN10−, VIN10+ Input ADC 10 Analog Input Complement/True. H9, H10 VIN11−, VIN11+ Input ADC 11 Analog Input Complement/True. J9, K9 VIN12−, VIN12+ Input ADC 12 Analog Input Complement/True. J8, K8 VIN13−, VIN13+ Input ADC 13 Analog Input Complement/True. J7, K7 VIN14−, VIN14+ Input ADC 14 Analog Input Complement/True. J6, K6 VIN15−, VIN15+ Input ADC 15 Analog Input Complement/True. J5, K5 VIN16−, VIN16+ Input ADC 16 Analog Input Complement/True. J3, K3 CLK−, CLK+ Input Clock Input Complement/True. Digital Inputs J2, K2 SYSREF−, SYSREF+ Input Active High JESD204B LVDS/CML System Reference Input Complement/True. A2, A3 SYNCINB+, SYNCINB- Input Active Low JESD204B LVDS Sync Input True/Complement. H1, J1 TRIG+, TRIG− Input Trigger Input LVDS. These TRIG± pins can be left floating if disabled. Data Outputs D1, D2 SERDOUT0−, SERDOUT0+ Output Lane 0 Output Data Complement/True. E1, E2 SERDOUT1−, SERDOUT1+ Output Lane 1 Output Data Complement/True. F1, F2 SERDOUT2−, SERDOUT2+ Output Lane 2 Output Data Complement/True. G1, G2 SERDOUT3−, SERDOUT3+ Output Lane 3 Output Data Complement/True. Digital Controls C5 PD/STBY Input Power-Down Input (Active High). The operation of the PD/STBY pin depends on the SPI mode and can be configured as power-down or standby. D5 RSTB Input Active Low Input for Device Reset. A4 CSB Input SPI Chip Select (Active Low). B4 SCLK Input SPI Serial Clock. C4 SDIO Input/output SPI Serial Data Input/Output. |
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