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AD9083BBCZ Datasheet(PDF) 6 Page - Analog Devices |
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AD9083BBCZ Datasheet(HTML) 6 Page - Analog Devices |
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6 / 93 page  AD9083 Data Sheet Rev. 0 | Page 6 of 93 AC Specifications for Different Variable Settings See the AN-835 for definitions and for details on how the tests shown in this section were completed. fS is the sample clock of the converter core. Backoff is the reduction in front-end gain for increased linearity. EN_HP increases the SNR by 2.5 dB at an increased power dissipation. Table 4. Variable Settings: fS = 2.0 GSPS, Backoff = 0, and EN_HP = 0 Parameters Test Conditions/Comments Min Typ Max Unit NSD Flicker Noise Corner 1 MHz At 15.625 MHz (fS/128) AIN = −2.0 dBFS −155 dBFS/Hz At 31.25 MHz (fS/64) AIN = −2.0 dBFS −153 dBFS/Hz At 100 MHz (fS/20) AIN = −2.0 dBFS −145 dBFS/Hz SNR AIN = −2.0 dBFS 7.8 MHz to 23.4 MHz (15.625 MHz Bandwidth) 82 dBFS 23.4 MHz to 39 MHz (15.625 MHz Bandwidth) 80 dBFS 92.2 MHz to 107.8 MHz (15.625 MHz Bandwidth) 71 dBFS DC to 15.625 MHz 82 dBFS DC to 31.25 MHz 76 dBFS DC to 100 MHz 66 dBFS SFDR/HD3 AIN = −2.0 dBFS At fS/128 −80 dBc At fS/64 −75 dBc At fS/20 −60 dBc IMD3 AIN = −8.0 dBFS At fS/128 −80 dBc At fS/64 −75 dBc At fS/20 −60 dBc Table 5. Variable Settings: fS = 2.0 GSPS, Backoff = 3, and EN_HP = 0 Parameters Test Conditions/Comments Min Typ Max Unit NSD Flicker Noise Corner 1 MHz At 15.625 MHz (fS/128) AIN = −2.0 dBFS −153 dBFS/Hz At 31.25 MHz (fS/64) AIN = −2.0 dBFS −151 dBFS/Hz At 100 MHz (fS/20) AIN = −2.0 dBFS −143 dBFS/Hz SNR AIN = −2.0 dBFS 7.8 MHz to 23.4 MHz (15.625 MHz Bandwidth) 80 dBFS 23.4 MHz to 39 MHz (15.625 MHz Bandwidth) 74 dBFS 92.2 MHz to 107.8 MHz (15.625 MHz Bandwidth) 64 dBFS DC to 15.625 MHz 80 dBFS DC to 31.25 MHz 74 dBFS DC to 100 MHz 64 dBFS SFDR/HD3 AIN = −2.0 dBFS At fS/128 −81 dBc At fS/64 −78 dBc At fS/20 −63 dBc IMD3 AIN = −8.0 dBFS At fS/128 −81 dBc At fS/64 −77 dBc At fS/20 −63 dBc |
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