| Electronic Components Datasheet Search |
|
AD9083BBCZ Datasheet(PDF) 11 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9083BBCZ Datasheet(HTML) 11 Page - Analog Devices |
|
11 / 93 page ![]() Data Sheet AD9083 Rev. 0 | Page 11 of 93 SWITCHING SPECIFICATIONS AVDD = 1.0 V, AVDD1P8 = 1.8 V, DVDD = 1.0 V, DVDD1P8 = 1.8 V, VMAX = 1.8 V1, −40°C ≤ TJ ≤ +115°C2, mode details as shown in Table 13, unless otherwise noted. Typical specifications represent performance at TJ = 45°C (TA = 25°C). Table 13. Parameter Min Typ Max Unit CLOCK Clock Rate (at CLK+/CLK− Pins)4 50 250 500 MHz ADC Sample Rate5 1 2 GSPS Clock Pulse Width 1 10 ns OUTPUT PARAMETERS Unit Interval (UI)6 62.5 4000 ps Rise Time (tR) (20% to 80% into 100 Ω Load) 30 ps Fall Time (tF) (20% to 80% into 100 Ω Load) 30 ps Phase-Locked Loop (PLL) Lock Time7 5 ms Data Rate per Channel (NRZ)8 0.25 16 Gbps 1 VMAX is the programmable maximum ADC input voltage range. 2 The TJ range of −40°C to +115°C translates to an TA range of −65°C to +85°C. 3 16-channel 125 MSPS real output mode. 4 Input clock to the on-chip PLL (Pin K3 and Pin J3). 5 ADC sample clock of the converter core. 6 Baud rate = 1/UI. A subset of this range can be supported. 7 Lock times may vary depending on the JESD204B link setup. 8 Default L = 4. This number can be changed based on the sample rate and decimation ratio. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |