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AD9083BBCZ Datasheet(PDF) 12 Page - Analog Devices |
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AD9083BBCZ Datasheet(HTML) 12 Page - Analog Devices |
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12 / 93 page  AD9083 Data Sheet Rev. 0 | Page 12 of 93 TIMING SPECIFICATIONS Table 14. Parameter Description Min Typ Max Unit SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 4 ns tDH Hold time between the data and the rising edge of SCLK 4 ns tCLK Period of the SCLK 10 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK must be in a logic high state 4 ns tLOW Minimum period that SCLK must be in a logic low state 4 ns tACCESS Maximum time delay between falling edge of SCLK and output data valid for a read operation 2 4 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 6 ns CSB SCLK SDIO tS tDH tLOW tDS tHIGH tCLK tACCESS tH A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 A14 R/W DON’T CARE DON’T CARE DON’T CARE DON’T CARE Figure 2. Serial Port Interface Timing Diagram |
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