AXM0F243 datasheet(30/53 Pages) ONSEMI

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AXM0F243

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MICROCONTROLLER

CPU and Memory Subsystem

CPU

The Cortex−M0+ CPU in the AXM0F243 is part of the

32−bit MCU subsystem, which is optimized for low−power

operation with extensive clock gating. Most instructions are

16 bits in length and the CPU executes a subset of the

Thumb−2 instruction set. It includes a nested vectored

interrupt controller (NVIC) block with eight interrupt inputs

and also includes a Wakeup Interrupt Controller (WIC). The

WIC can wake the processor from Deep Sleep mode,

allowing power to be switched off to the main processor

when the chip is in Deep Sleep mode.

The CPU also includes a debug interface, the serial wire

debug (SWD) interface, which is a two−wire form of JTAG.

The debug configuration used for AXM0F243 has four

breakpoint (address) comparators and two watchpoint (data)

comparators.

Flash

The AXM0F243 device has a flash module with a flash

accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The low−power flash

block is designed to deliver two wait−state (WS) access time

at 48 MHz. The flash accelerator delivers 85% of

single−cycle SRAM access performance on average.

SRAM

Eight KB of SRAM are provided with zero wait−state

access at 48 MHz.

System Resources

Power System

The power system is described in detail in the section

“Power”. It provides assurance that voltage levels are as

required for each respective mode and either delays mode

entry (for example, on power−on reset (POR)) until voltage

levels are as required for proper functionality, or generates

resets (for example, on brown−out detection). The

AXM0F243 operates with a single external supply over the

range of 1.8 to 3.6 V (internally regulated) and has three

different power modes, transitions between which are

managed by the power system. The AXM0F243 provides

Active, Sleep, and Deep Sleep low−power modes.

All subsystems are operational in Active mode. The CPU

subsystem (CPU, flash, and SRAM) is clock−gated off in

Sleep mode, while all peripherals and interrupts are active

with instantaneous wake−up on a wake−up event. In Deep

Sleep mode, the high−speed clock and associated circuitry

is switched off; wake−up from this mode takes 35

ms. The

opamps can remain operational in Deep Sleep mode.

Clock System

The AXM0F243 clock system is responsible for

providing clocks to all subsystems that require clocks and

for switching between different clock sources without

glitching. In addition, the clock system ensures that there are

no metastable conditions.

The clock system for the AXM0F243 consists of the

internal main oscillator (IMO), internal low−frequency

oscillator (ILO), a 32 kHz Watch Crystal Oscillator (WCO)

and provision for an external clock. Clock dividers are

provided to generate clocks for peripherals on a

fine−grained basis. Fractional dividers are also provided to

enable clocking of higher data rates for UARTs.

Figure 5. AXM0F243 MCU Clocking Architecture

The HFCLK signal can be divided down to generate

synchronous clocks for the analog and digital peripherals.

There are eight clock dividers for the AXM0F243; two of

those are fractional dividers. The 16−bit capability allows

flexible generation of fine−grained frequency values.

The IMO is the primary source of internal clocking in the

AXM0F243. It is trimmed during testing to achieve the

specified accuracy.The IMO default frequency is 24 MHz

and it can be adjusted from 24 to 48 MHz in steps of 4 MHz.

The IMO tolerance with provided calibration settings is

±2%.

ILO Clock Source

The ILO is a very low power, nominally 40−kHz

oscillator, which is primarily used to generate clocks for the

watchdog timer (WDT) and peripheral operation in Deep

Sleep mode.

Watch Crystal Oscillator (WCO)

The AXM0F243 clock subsystem also implements a

low−frequency (32−kHz watch crystal) oscillator that can be

used for precision timing applications.

Watchdog Timer

A watchdog timer is implemented in the clock block

running from the ILO; this allows watchdog operation

during Deep Sleep and generates a watchdog reset if not

serviced before the set timeout occurs. The watchdog reset

is recorded in a Reset Cause register, which is firmware

readable.

Reset

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