AXM0F243 datasheet(31/53 Pages) ONSEMI

31 / 53 page

AXM0F243

www.onsemi.com

The AXM0F243 can be reset from a variety of sources

including a software reset. Reset events are asynchronous

and guarantee reversion to a known state. The reset cause is

recorded in a register, which is sticky through reset and

allows software to determine the cause of the reset. An

XRES pin is reserved for external reset by asserting it active

low. The XRES pin has an internal pull−up resistor that is

always enabled.

Analog Blocks

12−bit SAR ADC

The 12−bit, 1−Msps SAR ADC can operate at a maximum

clock rate of 18 MHz and requires a minimum of 18 clocks

at that frequency to do a 12−bit conversion.

The Sample−and−Hold (S/H) aperture is programmable

allowing the gain bandwidth requirements of the amplifier

driving the SAR inputs, which determine its settling time, to

be relaxed if required. It is possible to provide an external

bypass (through a fixed pin location) for the internal

reference amplifier.

The SAR is not available in Deep Sleep mode as it requires

a high−speed clock (up to 18 MHz). The SAR operating

range is 1.8 V to 3.6 V.

Two Opamps (Continuous−Time Block; CTB)

The AXM0F243 has two opamps with Comparator modes

which allow most common analog functions to be

performed on−chip eliminating external components;

PGAs, Voltage Buffers, Filters, Trans−Impedance

Amplifiers, and other functions can be realized, in some

cases with external passives. saving power, cost, and space.

The on−chip opamps are designed with enough bandwidth

to drive the Sample−and−Hold circuit of the ADC without

requiring external buffering.

Low−power Comparator (LPC)

The AXM0F243 has a low−power comparator, which can

also operate in Deep Sleep modes. This allows the analog

system blocks to be disabled while retaining the ability to

monitor external voltage levels during low−power modes.

The comparator outputs are normally synchronized to avoid

metastability unless operating in an asynchronous power

mode where the system wake−up circuit is activated by a

comparator switch event. The LPC outputs can be routed to

pins.

Current DACs

The AXM0F243 has two IDACs, which can drive any of

the pins on the chip. These IDACs have programmable

current ranges.

Analog Multiplexed Buses

The AXM0F243 has two concentric independent buses

that go around the periphery of the chip. These buses (called

amux buses) are connected to firmware−programmable

analog switches that allow the chip’s internal resources

(IDACs, comparator) to connect to any pin on the I/O Ports.

Programmable Digital Blocks

The Programmable I/O (Smart I/O) block is a fabric of

switches and LUTs that allows Boolean functions to be

performed in signals being routed to the pins of a GPIO port.

The Smart I/O can perform logical operations on input pins

to the chip and on signals going out as outputs.

Fixed Function Digital

Timer/Counter/PWM (TCPWM) Block

The TCPWM block consists of a 16−bit counter with

user−programmable period length. There is a capture

(which may be an I/O event), a period register that is used to

either stop or auto−reload the counter when its count is equal

to the period register, and compare registers to generate

compare value signals that are used as PWM duty cycle

outputs. The block also provides true and complementary

outputs with programmable offset between them to allow

use as dead−band programmable complementary PWM

outputs. It also has a Kill input to force outputs to a

predetermined state; for example, this is used in motor drive

systems when an over−current state is indicated and the

PWM driving the FETs needs to be shut off immediately

with no time for software intervention. There are five

TCPWM blocks in the AXM0F243.

Serial Communication Block (SCB)

The AXM0F243 has three serial communication blocks,

which can be programmed to have SPI, I2C, or UART

functionality.

I2C Mode: The hardware I2C block implements a full

multi−master and slave interface (it is capable of

multi−master arbitration). This block is capable of operating

at speeds of up to 400 kbps (Fast Mode) and has flexible

buffering options to reduce interrupt overhead and latency

for the CPU. It also supports EZI2C that creates a mailbox

address range in the memory of the AXM0F243 and

effectively reduces I2C communication to reading from and

writing to an array in memory. In addition, the block

supports an 8−deep FIFO for receive and transmit which, by

increasing the time given for the CPU to read data, greatly

reduces the need for clock stretching caused by the CPU not

having read data on time.

The I2C peripheral is compatible with the I2C

Standard−mode and Fast−mode devices as defined in the

NXP I2C−bus specification and user manual (UM10204).

The I2C bus I/O is implemented with GPIO in open−drain

modes.

The AXM0F243 is not completely compliant with the I2C

spec in the following respect:

• GPIO cells are not overvoltage tolerant and, therefore,

cannot be hot−swapped or powered up independently of

the rest of the I2C system.

UART Mode: This is a full−feature UART operating at up

to 1 Mbps. It supports automotive single−wire interface

AXM0F243 Datasheet(PDF) 31 Page - ON Semiconductor

AXM0F243 Datasheet(HTML) 31 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL