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8104 Datasheet(PDF) 21 Page - LSI Computer Systems |
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8104 Datasheet(HTML) 21 Page - LSI Computer Systems |
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21 / 172 page ![]() Figure 2.1 8101/8104 Block Diagram REGCSn RESETn SCLK TXENn TXD[31:0] TXBE[3:0] TXSOF TXEOF TXWM1n TXWM2n TXDC CLR_TXDC TXCRCn RXENn RXD[31:0] RXBE[3:0] RXSOF RXEOF RXWM1 RXWM2 RXDC CLR_RXDC RXABORT RXOEn REGCLK REGD[15:0] REGAD[7:0] REGRDn REGWRn REGINT System Interface Register Interface & Registers Transmit FIFO Packet Generator Receive FIFO Management Counters CRC Generator MAC Control Frame Gen. MAC 8B10B Encoder Transmit 8B10B PCS Packet Decompose MAC Control Frame Check Address Filter CRC Check Receive Transmit Receive Transmit 8B10B Decoder Link Configuration Receive Receive Sync. TCLK 10-Bit PHY Interface TX[9:0] TBC EWRAP EN_CDET LCK_REFn SD LINKn RX[0:9] RBC[1:0] FCNTRL |
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