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8104 Datasheet(PDF) 4 Page - LSI Computer Systems |
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8104 Datasheet(HTML) 4 Page - LSI Computer Systems |
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4 / 172 page ![]() iv Preface Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. • Chapter 3, Signal Descriptions, provides a description of the signals used and generated by the 8101/8104 Gigabit Ethernet Controller. • Chapter 4, Registers, provides a description of the register addresses and definitions. • Chapter 5, Application Information, provides application considerations. • Chapter 6, Specifications, describes the specifications of the 8101/8104 Gigabit Ethernet Controller. Abbreviations Used in This Manual 100BASE-FX 100 Mbit/s Fiber Optic Ethernet 100BASE-TX 100 Mbit/s Twisted-Pair Ethernet 10BASE-T 10 Mbit/s Twisted-Pair Ethernet 4B5B 4-Bit 5-Bit BGA Ball Grid Array CLK Clock CRC Cyclic Redundancy Check CRS Carrier Sense CSMA Carrier Sense Multiple Access CWRD Codeword DA Destination Address ECL Emitter-Coupled Logic EOF End of Frame ESD End of Stream Delimiter FCS Frame Check Sequence FDX Full-Duplex FEF Far End Fault FLP Fast Link Pulse FX Fiber HDX Half-Duplex HIZ High Impedance I/G Individual/Group IETF Internet Engineering Task Force IPG Interpacket Gap IREF Reference Current L/T Length and Type LSB Least Significant Bit |
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