LTC7151S datasheet(12/38 Pages) AD

12 / 38 page

LT7182S

Rev. 0

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PIN FUNCTIONS

PVIN1 (Pins 15, 18): Power Supply Input for Channel 1.

These pins must be tied together and bypassed as close

as possible to the LT7182S, with a low ESR capacitor of

value 4.7µF or more.

SW1 (Pins 16, 17, Exposed Pad Pin 44): Output of the

Channel1 Internal Power Switches. Tie these pins together

and connect them to the channel1 inductor and BOOST1

capacitor. This node should be kept small on the PCB for

good performance.

DRVCC (Pin 20): Internal 3.5V LDO Regulator Bypass.

This regulator provides the supply current for the power

FET drivers. This pin must be bypassed to PGND with a

10µF or greater, low ESR ceramic capacitor, as close as

possible to the IC, using the top PCB layer. Do not load

the DRVCC pin with external circuitry, with the optional

exceptions of the pull-up resistor for the SHARE_CLK pin

and/or the RUN0, RUN1, FAULT0, or FAULT1 pins.

EXTVCC (Pin 21): Optional Power Supply Input. If con-

nected to 3V to 5.5V, this pin will be used to derive the

DRVCC, INTVCC, and VDD18 supplies. If one of the regulator

outputs is set to VOUT of 3V or greater, that VOUT may be

connected to EXTVCC to reduce power loss. If this pin is

not tied to a regulator output, use a 0.1μF or greater local

bypass ceramic capacitor on this pin, as close as possible

to the LT7182S.

SYNC/PWM_CFG (Pin 22): External Clock Synchronization

Input/Output and/or PWM Configuration. When driven

with an external clock, an internal phase-locked loop syn-

chronizes the switching regulator output with the rising

edge of the external clock. If this pin is to be used as

a clock input, then a 1.5nF AC-coupling capacitor must

be inserted in series with the clock source, unless the

EEPROM is programmed to ignore the configuration

resistors (MFR_CONFIG_ALL_LT7182S bit 6 set) in which

case the clock source can be connected directly. If config-

ured as an output (MFR_SYNC_CONFIG_LT7182S bit 0

set), the LT7182S will drive the SYNC/PWM_CFG pin out-

put at the switching clock frequency set by FREQUENCY_

SWITCH, with a voltage swing of 0V to 1.88V (typical).

Connect a 1% resistor from SYNC/PWM_CFG to ground

(PGND or SGND) according to Table 3 in Applications

Information to select frequency, phase, and mode con-

figurations. The SYNC/PWM_CFG pin is read at LT7182S

startup and reset. See Applications Information for more

details.

RUN0, RUN1 (Pin 24, Pin 23): Regulator Enable Inputs.

Logic high enables the regulators. The RUN0 and RUN1

pins are pulled down with 1.5mA (typical) during POR

and reset to facilitate sequencing with other regulators,

but may be over-driven high by a digital output of another

device. The pins may be tied directly to DRVCC to enable

the regulators when input power is present.

SHARE_CLK (Pin 25): Bidirectional Open-Drain Sequence

Time Base Share Clock. Nominally 100kHz. Used to align

startup and shutdown of regulator outputs among multiple

ADI products when PolyPhase or time-based sequencing

is employed. A pull-up resistor to 1.6V to 5.5V is required

if the SHARE_CLK function is used. If neither PolyPhase

nor time-based sequencing are required, SHARE_CLK

may be tied to ground if bit 2 of MFR_CHAN_CONFIG_

LT7182S is programmed to zero for both channels (to

ignore SHARE_CLK).

WP (Pin 26): Write Protect Input. When this pin is high,

only the PAGE, OPERATION, MFR_EE_UNLOCK, and

CLEAR_FAULTS commands are writable. Clear individ-

ual fault bits by writing a 1 to the respective bits in the

STATUS commands.

LTC7151S Datasheet(PDF) 12 Page - Analog Devices

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