LTC7151S datasheet(21/38 Pages) AD

21 / 38 page

LT7182S

Rev. 0

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APPLICATIONS INFORMATION

If the VOUTn_CFG pin is open or tied to VDD18, the VOUT_

COMMAND command is loaded from EEPROM to deter-

mine the output voltage. The default EEPROM setting is

to initialize with the regulator disabled unless the voltage

configuration resistors are installed.

The following commands are initialized based on a per-

centage of VOUT_COMMAND if the resistor configuration

pins are used to initialize the output voltage:

• VOUT_OV_FAULT_LIMIT

+10%

• VOUT_OV_WARN_LIMIT

+7.5%

• VOUT_MAX

+7.5%

• VOUT_MARGIN_HIGH

+5%

• VOUT_MARGIN_LOW

–5%

• VOUT_UV_WARN_LIMIT

–6.5%

• VOUT_UV_FAULT_LIMIT

–7%

SWITCHING FREQUENCY AND PHASE

The PWM switching frequency can be established using

the internal oscillator or applying an external clock on

the SYNC/PWM_CFG pin. An internal phase-locked loop

(PLL) synchronizes PWM control to this timing reference,

whether the clock is provided internally or externally. The

internal oscillator frequency is set by the FREQUENCY_

SWITCH command. The MFR_PWM_PHASE_LT7182S

command configures the phase of each channel.

The SYNC/PWM_CFG pin is a flexible multi-purpose input/

output pin, which can be used as a configuration resistor

input as well as a clock input or output.

A configuration resistor connected between SYNC/PWM_

CFG and ground (PGND or SGND) may be used to initial-

ize PWM configuration (including frequency, phase, and

operating mode) according to Table 3. See Figure 1 for

an example of PWM configuration resistor connection

for single- and dual-phase applications where no exter-

nal synchronization input or output clock is required. See

Table 2 for PWM_CFG resistor selection options.

The LT7182S will automatically synchronize PWM switch-

ing to an external clock input on SYNC/PWM_CFG, unless

the LT7182S has been configured as an output driver or

has been programmed to ignore the input clock. When

an external synchronization clock is used on the SYNC/

PWM_CFG pin, the LT7182S automatically uses forced

continuous mode on both channels. The LT7182S will

continue PWM operation using its own internal oscilla-

tor if the external clock signal is lost. If an external syn-

chronization clock is to be used, it is recommended to

program the FREQUENCY_SWITCH command or to use

a configuration resistor to set the internal oscillator fre-

quency to a similar value to the external clock frequency.

This ensures that the PWM switching frequency remains

reasonable if the external clock is lost. The LT7182S can

be programmed to ignore an external clock by writing a

1 to bit 1 of MFR_SYNC_CONFIG_LT7182S.

The LT7182S can be configured to provide a synchronizing

clock output on the SYNC/PWM_CFG pin to other devices

by setting bit 0 of MFR_SYNC_CONFIG_LT7182S to 1.

If the SYNC/PWM_CFG output clock is enabled, the

LT7182S will drive the SYNC/PWM_CFG pin as a square

wave from 0 to 1.88V (typical) at the frequency pro-

grammed in FREQUENCY_SWITCH. The phase of SYNC

will lead the phase of the PWM output by the value set in

the MFR_PWM_PHASE_LT7182S command. Only one

device connected to SYNC/PWM_CFG may be configured

as an output.

When a clock is active on SYNC/PWM_CFG, the MFR_

PWM_PHASE_LT7182S command specifies the phase

relationship between the rising edge of SYNC/PWM_CFG

and the rising edge of SW for the channel.

If both the SYNC/PWM_CFG configuration resistor and

synchronization clock input functions are utilized, the

clock signal must be AC-coupled using a 1.5nF capacitor

between the clock source and the LT7182S, as shown in

Figure 2. In this case, the clock signal must be inactive

during LT7182S initialization to ensure it does not interfere

with the resistor configuration function. If the AC-coupled

clock source output impedance is less than 50Ω, a 50Ω

Figure 1. PWM Resistor Configuration with No External Clock

7182s F01

SYNC/PWM_CFG

LT7182S

RPWM_CFG

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