LTC7151S datasheet(20/38 Pages) AD

20 / 38 page

LT7182S

Rev. 0

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USING RESISTOR CONFIGURATION PINS

The LT7182S has four resistor configuration pins each

utilizing a single ±1% resistor to select key operating

parameters. The resistor configuration pins are ASEL,

VOUT0_CFG, VOUT1_CFG/POLYPHASE_CFG, and SYNC/

PWM_CFG. The resistor configuration pins are measured

upon power-up and execution of a RESTORE_USER_ALL

or MFR_RESET command. The function of each resistor

configuration pin is described in the sections below.

If bit 6 of the MFR_CONFIG_ALL_LT7182S command

is set to 1 in EEPROM, the configuration resistors are

ignored on CFG pins VOUT0_CFG, VOUT1_CFG/POLYPHASE_

CFG, and SYNC/PWM_CFG, while the ASEL resistor is

always respected.

See the MFR_ADDRESS command in the LT7182S

PMBus/I2C Reference Manual for information about

APPLICATIONS INFORMATION

setting the serial interface device address including ASEL

configuration resistor selection.

SETTING OUTPUT VOLTAGE

The VOUT_COMMAND PMBus command specifies the

output voltage when the channel is enabled.

VOUT_COMMAND can be initialized using resistors on the

VOUT0_CFG and VOUT1_CFG/POLYPHASE_CFG pins, based

on the values in Table 2. A resistor between VOUT0_CFG

and SGND configures channel 0. If channel 1 is config-

ured as an independent output from channel 0, then a

resistor between the VOUT1_CFG/POLYPHASE_CFG pin and

SGND configures channel 1. If PolyPhase configuration

is selected (by connecting a 5.6k ±10% resistor between

SYNC/PWM_CFG and ground) then VOUT0_CFG configures

both channels 0 and 1.

Table 2. VOUTn_CFG Pin Configuration Resistor Selection (Note 1)

RESISTOR VALUE (±1%)

OUTPUT VOLTAGE SET POINT (V) (Note 2)

VOUT RANGE MODE (Note 3)

REGULATOR ENABLE (Note 4)

Floating or VDD18

Initialized from NVM (Default 0.5V)

Initialized from NVM (Default full

VOUT range).

Initialized from NVM (By default, regulator

is enabled if RUN pin is asserted high.)

124kΩ

Full VOUT range. Supports

0.4V ≤ VOUT ≤ 5.5V.

Regulator is enabled if RUN is

asserted high.

(OPERATION = 0x80. ON_OFF_CONFIG

initialized from NVM, default requires

OPERATION = 0x80 and RUN pin

asserted.)

107kΩ

3.3

93.1kΩ

2.5

80.6kΩ

1.8

69.8kΩ

1.5

60.4kΩ

1.35

51.1kΩ

1.2

High-performance

Low-VOUT range.

Offers enhanced accuracy and

transient response for

VOUT ≤ 1.375V.

43.2kΩ

1.1

36.5kΩ

30.9kΩ

0.9

25.5kΩ

0.85

21kΩ

0.8

16.5kΩ

0.75

11.8kΩ

0.7

6.65kΩ

0.6

0 (SGND)

Initialized from NVM (Default 0.5V)

Initialized from NVM (default full

VOUT range)

Regulator disabled and RUN pin ignored.

Note 1. If the SYNC/PWM_CFG pin is connected to a 5.6kΩ ±10% resistor to select Polyphase operation as per Table 3, then the

VOUT1_CFG/POLYPHASE_CFG configuration resistor controls PWM settings including frequency and phase per Table 4.

Note 2. Output voltage set point is controlled by VOUT_COMMAND.

Note 3. VOUT Range Mode selection is controlled by MFR_PWM_MODE_LT7182S bit 1. A value of 1 selects High-Performance Low-VOUT mode.

Note 4. The PMBus ON_OFF_CONFIG command selects whether the RUN pin and/or PMBus OPERATION command enable the regulator.

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