LTC7151S datasheet(22/38 Pages) AD

22 / 38 page

LT7182S

Rev. 0

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APPLICATIONS INFORMATION

Table 3. SYNC/PWM_CFG Pin Configuration Resistor Selection

RESISTOR

VALUE

(±1%)

PWM

FREQUENCY

(Notes 1, 2)

PWM PHASE

(Note 3)

PWM MODE

(Note 4)

PolyPhase

FOLLOWER/

LEADER

(Note 5)

INTERNAL COMPENSATION

(Note 6)

SYNC/PWM_CFG

CLOCK

OUTPUT OR

INPUT

(Note 8)

Ch 0

Ch 1

INTERNAL

CITH

INTERNAL

RITH

INTERNAL

gMEA

162kΩ

Initialized from

NVM

(Default 1MHz)

Initialized

from NVM

(Default 0°)

Initialized

from NVM

(Default 180°)

Initialized

from NVM

(Default FCM)

Initialized

from NVM

(Default 0,

Leader)

Initialized

from NVM

(Default 80pF)

Initialized from

NVM

(Default 20kΩ)

Initialized

from NVM

(Note 7)

Initialized from

NVM

(Default 0, Input)

124kΩ

500kHz

0°

180°

FCM

(Leader)

80pF

20kΩ

150µS

0 (Input)

80.6kΩ

1MHz

80pF

40kΩ

51.1kΩ

2MHz

80pF

40kΩ

30.9kΩ

4MHz

60pF

40kΩ

107 kΩ

500kHz

90°

270°

80pF

20kΩ

69.8kΩ

1MHz

80pF

40kΩ

43.2kΩ

2MHz

80pF

40kΩ

93.1kΩ

500kHz

0°

180°

Pulse-skip

80pF

20kΩ

60.4kΩ

1MHz

80pF

40kΩ

36.5kΩ

2MHz

80pF

40kΩ

Clock

Active

Throughout

POR and

Reset

Measured at

POR/Reset

0°

180°

FCM

NVM

(Default 0,

Leader)

(Note 9)

5.6kΩ

±10%

PolyPhase Configuration Select: PWM Configuration is controlled by the VOUT1_CFG/POLYPHASE_CFG pin, as indicated in Table 4. In this

configuration, VOUT for both channels is initialized to the value specified by the VOUT0_CFG resistor.

Note 1. PWM Switching frequency set point is controlled by FREQUENCY_SWITCH, if no SYNC/PWM_CFG input clock is present.

Note 2. If an external synchonrization clock is used as well as a configuration resistor, the clock source must be AC-coupled with a 1.5nF series capacitor,

and the clock source must be inactive during initialization of the LT7182S. The configuration resistor value should be chosen to set the internal PWM

switching frequency to a similar value to the input clock.

Note 3. Steady-State PWM Switching Phase is controlled by MFR_PWM_PHASE_LT7182S.

Note 4. PWM Mode is controlled by MFR_PWM_MODE_LT7182S bit 0. A value of 1 enables pulse-skip mode.

Note 5. Poly-phase follower/leader mode is controlled by MFR_CHAN_CONFIG_LT7182S bit 8. A value of 1 selects follower mode.

Note 6. Internal compensation is selected by tying ITH to INTVCC. For PWM_CFG resistor values ≤ 124kΩ, if external compensation is used, gmEA is set to

the maximum value (1.2mS for High-Performance Low-VOUT mode; 300µS for Standard mode). For internal compensation, CITH is controlled by MFR_

PWM_MODE_LT7182S bits [8:6], and RITH is controlled by MFR_PWM_MODE_LT7182S bits [5:3]. gmEA is controlled by MFR_PWM_MODE_LT7182S

bits [13:11].

Note 7. The NVM default for MFR_PWM_MODE_LT7182S bits [11:9] is 0b011, which corresponds to gmEA = 600µS for High-Performance Low-VOUT

mode and gmEA = 150µS for Standard mode, regardless of internal or external compensation.

Note 8. The SYNC/PWM_CFG pin is a clock output when MFR_SYNC_CONFIG_LT7182S bit 0 is set to 1.

Note 9. When an external clock is detected during POR/reset of the LT7182S, internal compensation parameters CITH and RITH are chosen based on the

measured external clock frequency:

• 400kHz to 625kHz: RITH = 20kΩ, CITH = 80pF

• 625kHz to 1.25MHz: RITH = 40kΩ, CITH = 80pF

• 1.25MHz to 2.5MHz: RITH = 40kΩ, CITH = 80pF

• 2.5MHz to 4MHz: RITH = 40kΩ, CITH = 60pF

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