LTC7151S datasheet(23/38 Pages) AD

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LT7182S

Rev. 0

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APPLICATIONS INFORMATION

resistor must be added in series with the clock source.

See Table 2 for PWM_CFG resistor selections.

For an input clock frequency of 400kHz to 625kHz, it is

recommended to use a configuration resistor that selects

a PWM frequency of 500kHz. For an input clock frequency

of 625kHz to 1.25MHz, it is recommended to use a con-

figuration resistor that selects a PWM frequency of 1MHz.

For an input clock frequency of 1.25MHz to 2.5MHz, it is

recommended to use a configuration resistor that selects

a PWM frequency of 2MHz. For an input clock frequency

of 2.5MHz to 4MHz, it is recommended to use a config-

uration resistor that selects a PWM frequency of 4MHz.

If the SYNC/PWM_CFG pin is used only as a clock input

or output and MFR_CONFIG_ALL_LT7182S bit 6 has been

written to 1 in EEPROM to disable CFG pins, then no con-

figuration resistor or AC-coupling capacitor is required.

If an external clock is applied to the SYNC/PWM_CFG pin

throughout initialization, and the CFG pin function has not

been disabled, the LT7182S measures the clock frequency

and initializes FREQUENCY_SWITCH to the measured

frequency rounded to the nearest 100kHz. In this case,

channel 0 MFR_PWM_PHASE is initialized to 0 degrees

and channel 1 to 180 degrees and forced continuous

mode is selected. Note that, unless CFG pin functionality

has been disabled, an external clock applied to SYNC/

PWM_CFG must be either active or inactive throughout

the entire LT7182S initialization process. If the clock

activity changes during initialization, for example if the

clock starts after initialization begins but before it com-

pletes, the frequency measurement may be inaccurate

which could lead to the LT7182S incorrectly initializing

FREQUENCY_SWITCH or declaring a pin configuration

fault. See MFR_PIN_CONFIG_STATUS in the LT7182S

PMBus/I2C Reference Manual for more information

regarding pin configuration faults.

Figure 2. PWM Resistor Configuration and an External

Synchronization Clock

PolyPhase Load Sharing

Multiple LT7182S channels can be connected in parallel

to provide a balanced PolyPhase load-share solution. The

analog current mode control architecture of the LT7182S

ensures that load-sharing remains balanced among the

PolyPhase channels.

The corresponding ITH, FAULT, PVIN, VSENSEP and VSENSEN

pins must be connected among all PolyPhase channels,

and the SYNC/PWM_CFG and SHARE_CLK pins must

be connected among all PolyPhase devices. The phases

should be separated by 360/n degrees, where n is the

number of phases in the PolyPhase array. In PolyPhase,

exactly one device, either an LT7182S or an external clock

source, must be configured to drive a clock on SYNC/

PWM_CFG.

In a PolyPhase array, exactly one LT7182S channel must

be configured as a leader (MFR_CHAN_CONFIG_LT7182S

bit 8 value of 0), and all other PolyPhase channels must

be configured as followers (value set to 1).

PolyPhase mode can be selected by connecting a 5.6k

±10% resistor from SYNC/PWM_CFG to ground if MFR_

CONFIG_ALL_LT7182S bit 6 is not set to ignore CFG pins.

Resistor configuration options are available to support 2,

3, 4, or 6 phase PolyPhase solutions. When a 5.6k resistor

is connected on SYNC/PWM_CFG, VOUT_COMMAND for

channel 1 is set to the same value as channel 0 based on

the VOUT0_CFG resistor, and the VOUT1_CFG/POLYPHASE_

CFG resistor selects the PolyPhase configuration as

shown in Table 4. For 2, 4, or 6 phase operation, the SYNC/

PWM_CFG pins of up to three LT7182S devices may be

connected together to a single 5.6k resistor, as shown

in Figure 3. For two LT7182S devices configured for 3

phase + 1 phase operation, separate SYNC/PWM_CFG

configuration resistors are required along with a 1.5nF

AC-coupling capacitor between the devices, as shown

in Typical Applications. For PolyPhase arrays with 8 or

more phases, PMBus programming is required for at least

some of the devices, in order to set PolyPhase follower

mode (MFR_CHAN_CONFIG_LT7182S bit 8) and select

the appropriate phase (MFR_PWM_PHASE_LT7182S).

7182s F02

SYNC/PWM_CFG

NOTE: EXTERNAL CLOCKMUST BE INACTIVE

DURING LT7182S INITIALIZATION

EXTERNAL

CLOCK

RPWM_CFG

LT7182S

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