LTC7151S datasheet(13/38 Pages) AD

13 / 38 page

LT7182S

Rev. 0

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PIN FUNCTIONS

FAULT0, FAULT1 (Pin 28, Pin 27): Fault Input/Open-Drain

Outputs. The LT7182S pulls the pin down with 1.5mA

(typical) when an unmasked fault occurs on the regula-

tor. If another device pulls down on the FAULT pin, the

LT7182S regulator will turn off immediately. If PolyPhase

configuration is used, tie together the FAULT pins of all

PolyPhase channels. If PolyPhase configuration is used,

or if FAULT pin reporting or sharing is required, a pull-up

resistor of 6.8k or greater to 1.6V to 5.5V is required.

FAULT pins may be tied directly to DRVCC if the FAULT pin

function is not required.

ALERT (Pin 29): Open Drain Alert Output. If the ALERT

pin function is used, a pull-up resistor to 1.6V to 5.5V is

required. If the ALERT pin function is not used, the pin

may be tied to ground.

SCL (Pin 30): Serial Bus Clock Input and Output. The

LT7182S may hold SCL low if clock stretching is enabled

(PMBus speeds 400kHz-1MHz only). A pull-up resistor to

1.6V to 5.5V is required for PMBus/I2C operation. If serial

bus operation is not required, SCL may be tied to ground.

SDA (Pin 31): Serial Bus Data Input and Output. A pull-up

resistor to 1.6V to 5.5V is required for PMBus/I2C oper-

ation. If serial bus operation is not required, SDA may be

tied to ground.

PGOOD0, PGOOD1 (Pin 33, Pin 32): Power Good

Indicator Open-Drain Outputs. PGOOD is pulled low when

the regulator output is outside of the OV/UV fault thresh-

olds, when the channel is disabled, and during on/off

sequencing. The PGOOD output is deglitched by internal

configurable timers. If the PGOOD pin function is used, a

pull-up resistor to 1.6V to 5.5V is required. If the PGOOD

pin function is not used, these pins may tied to PGND.

PVIN0 (Pins 35, 38): Power Supply Input for Channel 0

and Internal LDO Regulators. These pins must be tied

together and bypassed to PGND as close as possible to

the LT7182S, with a low ESR capacitor of value 4.7µF or

more. If EXTVCC < 3V, then the internal LDO regulators

(for DRVCC, INTVCC, and VDD18) pull power from PVIN0.

SW0 (Pins 36, 37, Exposed Pad Pin 41): Output of the

Channel0 Internal Power Switches. Tie these pins together

and connect them to the channel0 inductor and BOOST0

capacitor. This node should be kept small on the PCB for

good performance.

BOOST0 (Pin 40): Boosted Floating Driver Supply.

Connect a 0.1µF boost capacitor from BOOST0 to SW0

as close as possible to the IC, using the top PCB layer.

The normal operation voltage swing of this pin is from

DRVCC to PVIN0+DRVCC.

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