LTC4261 datasheet(4/82 Pages) AD

4 / 82 page

LTC4284

Rev. B

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply

VIN

Shunt Regulated Voltage at VIN

IIN + IVZ = 4mA

10.8

11.5

∆VIN

Load Regulation at VIN

IIN + IVZ = 4mA to 35mA

250

500

IIN

VIN Supply Current

VIN = 10.5V

2.5

VIN(UVLO)

VIN Undervoltage Lockout Threshold

VIN Rising

7.5

8.1

8.6

∆VIN(UVLO)

VIN Undervoltage Lockout Hysteresis

0.4

0.5

0.6

IVZ

VZ Input Current

VIN = 10.5V, VZ = 15V

µA

INTVCC

Internal 5V LDO Voltage

ILOAD = 1mA to 30mA, IIN + IVZ = 35mA

4.75

5.05

5.35

VCC(UVLO)

INTVCC Undervoltage Lockout Threshold INTVCC Rising

3.65

4.3

∆VCC(UVLO)

INTVCC Undervoltage Lockout Hysteresis

0.12

0.2

0.3

Gate Drive

VGATE

Gate Drive Voltage for GATE1,2

VIN – 0.3

VIN

VIN + 0.3

VGATE(TH)

Gate High Threshold for Asserting Power

Good

GATE1,2 Rising

VIN – 2.1

VIN – 1.8

VIN – 1.5

VGATE(HYST)

Gate High Hysteresis

0.3

0.7

1.1

IGATE(UP)

GATE1,2 Pull-Up Current

VGATE = 4V

–40

–50

–75

µA

IGATE(DN)

GATE1,2 Fast Pull-Down Current

∆VSENSE1,2 = VILIM(FAST) + 10mV, VGATE = 7V l

0.5

1.2

GATE1,2 Current Limit Pull-Down Current ∆VSENSE1,2 = VILIM + 5mV, VGATE = 7V

12.5

GATE1,2 Turn Off Pull-Down Current

TMR, OV, EN# = High, UVL = Low, VGATE =

On/Off Timing

tPHL(SENSE)

∆VSENSE1,2 High to GATE1,2 Low

Propagation Delay

ILIM = 0000b, ∆VSENSE1,2 Steps from 0mV

to 100mV, VGATE < 3V, GATE1,2 Open

150

tPHL(GATE)

GATE1,2 Turn Off Propagation Delay

TMR, OV, EN# = High, UVL = Low, VGATE < 3V,

GATE1,2 Open

0.5

µs

tDL(DB)

Debounce Delay, Auto-Retry Delay

Following Undervoltage or PGI Fault

115

128

141

tDL(PG)

Power Good Delay

230

256

282

tDL(PGIWD)

Power Good Input Watchdog Timer

461

512

563

tDL(RTRY)

Auto-Retry Delay Following Overcurrent,

FET Bad or External Fault (Table 11)

COOLING_DL = 000b – 111b

±10

tDL(RTCRST)

Auto-Retry Counter Reset Delay

OC_RETRY, FET_BAD_RETRY = 01b, 10b

14.8

16.4

tDL(FETBAD)

FET Bad Fault Timer Delay (Table 11)

FTBD_DL = 00b – 11b

±10

tDL(RBT)

Auto-Reboot Delay (Table 23)

After RBT_EN Bit is Set Via I2C Interface,

RBT_DL = 000b – 111b

±10

dV/dt Control

IRAMP

RAMP Output Current

Startup Only, dV/dt Control Enabled

–2.25

–2.5

–2.75

µA

IRAMP(DN)

RAMP Discharge Current

VRAMP = 1.2V

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)

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