LTC4261 datasheet(8/82 Pages) AD

8 / 82 page

LTC4284

Rev. B

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All Currents into device pins are positive and all currents out

of device pins are negative. All voltages are referenced to VEE unless

otherwise specified.

Note 3: When VZ is connected to VIN, an internal shunt regulator limits the

voltage to a minimum of 11V. Driving the pins above 11V may damage the

part. These pins can be safely biased by a higher voltage using a resistor

or current source that limits the current below 50mA.

Note 4: An internal clamp limits DRAIN to a minimum of 3.2V. Driving

this pin to voltages above the clamp may damage the part. The pin can

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I2C Interface

VADR(H)

ADR0, ADR1 Input High Threshold

INTVCC

– 0.85

INTVCC

– 0.55

INTVCC

– 0.25

VADR(L)

ADR0, ADR1 Input Low Threshold

0.4

0.7

IADR(IN)

Allowable Leakage Current

±10

µA

VALERT#(OL)

ALERT# Output Low Voltage

I = 5mA

0.15

0.4

VSDAO(OL)

SDAO Output Low Voltage

I = 20mA

0.25

0.6

ISDAO,ALERT# SDAO, ALERT# Input Current

SDAO, ALERT# = INTVCC

±1

µA

VSDAI,SCL(TH) SDAI, SCL Input Threshold

1.5

1.75

ISDAI,SCL

SDAI, SCL Input Current

SDAI, SCL = INTVCC

±1

µA

I2C Interface Timing (Note 7)

fSCL(MAX)

Maximum SCL Clock Frequency

400

kHz

tLOW

Minimum SCL Low Period

0.65

1.3

µs

tHIGH

Minimum SCL High Period

600

tBUF(MIN)

Minimum Bus Free Time Between Stop/

Start Condition

0.12

1.3

µs

tHD,STA(MIN)

Minimum Hold Time After (Repeated)

Start Condition

140

600

tSU,STA(MIN)

Minimum Repeated Start Condition

Set-Up Time

600

tSU,STO(MIN)

Minimum Stop Condition Set-Up Time

600

tHD,DATI(MIN) Minimum Data Hold Time Input

–100

tHD,DATO(MIN) Minimum Data Hold Time Output

300

600

900

tSU,DAT(MIN)

Minimum Data Set-Up Time Input

100

tSP(MAX)

Maximum Suppressed Spike Pulse Width

110

250

tRST

Stuck-Bus Reset Time

SCL or SDAO Held Low

SCL, SDA Input Capacitance

SDAI Tied to SDAO

Single-Wire Broadcast Timing

fBC

Broadcast Data Rate (Table 11)

±10

EEPROM

Endurance

1 Cycle = 1 Write (Notes 8, 9)

10,000

Cycles

Data Retention

(Notes 8, 9)

Years

tWRITE

EEPROM Write Time per Byte

1.2

2.2

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)

be safely tied to higher voltages through a resistor that limits the current

below 1.5mA.

Note 5: An internal clamp limits EN# to a minimum of 6V. Driving this pin

to voltages above the clamp may damage the part. The pin can be safely

tied to higher voltages through a resistor that limits the current below

5mA.

Note 6: Guaranteed by design and characterization. Not tested in

production.

Note 7: Tested at 12-bit resolution and guaranteed for other resolutions by

design and characterization.

Note 8: EEPROM endurance and retention are guaranteed by design,

characterization and correlation with statistical process controls.

Note 9: EEPROM endurance and retention will be degraded when TJ > 85°C.

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