LTC4261 datasheet(24/82 Pages) AD

24 / 82 page

LTC4284

Rev. B

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APPLICATIONS INFORMATION

Power good signals are reset in two configurable ways.

If the PWRGD_RESET_CNTRL bit in CONTROL_1 reg-

ister 0x0A is set to 1, power good signals are reset by

an output low condition as indicated by RTNS − DRNS

< VOUTTH. In Figure 2a VOUTTH is biased at 0.8V, so

power good signals will be reset when RTNS – DRNS

drops below 0.8V, which corresponds to VOUT < 32V. If

the PWRGD_RESET_CNTRL bit is cleared, power good

signals are reset by any GATE turn-off conditions except

overvoltage fault. When the power good signals are reset,

the power good delays and the PGI delay are also reset.

Turn-Off Sequence

In any of the following conditions, the MOSFETs are

turned off by pulling down the GATE pins with 9mA cur-

rent sources and the FET_ON_STATUS bit in SYSTEM_

STATUS register 0x00 is cleared.

1. VIN is lower than 7.6V (VIN undervoltage lockout).

2. INTVCC is lower than 3.8V (INTVCC undervoltage

lockout).

3. EN# is high.

4. ON bit in CONTROL_1 register 0x0A is cleared.

5. OV is higher than 1.406V (overvoltage fault).

6. UVL is lower than 1.833V and UVH is lower than

2.048V (undervoltage fault).

7. TMR reaches its 2.048V threshold (overcurrent fault).

8. DRAIN rises above 2.048V or GATE dips below VIN

– 1.8V and this condition lasts longer than a pre-

configured delay (FET bad fault).

9. PGIO3, when configured as PGI#/PGI input, is high/

low when the PGI check delay of 512ms expires

(PGI fault).

10. PGIO4 pin, when configured as EXT_FAULT#/EXT_

FAULT, is low/high (external fault).

11. The RBT_EN bit in REBOOT register 0xA2 is set.

For condition 8, if the FET_BAD_TURN_OFF bit in

CONTROL_1 register 0x0A is cleared, the MOSFETs

remain on following a FET bad fault. For condition 10,

if the EXT_FAULT_TURN_OFF bit in CONFIG_3 register

0x0F is cleared, the MOSFETs remain on following an

external fault. For condition 11, the LTC4284 will auto-

matically reboot after a programmable delay. See Reboot

on I2C Command.

For each independent GATE turn-off fault, the LTC4284

can be configured to latch off the MOSFETs or go into

an auto-retry sequence after the fault occurs. In paral-

lel mode or single driver modes, GATE1 and GATE2 are

turned off simultaneously. In high stress or low stress

staged start modes, GATE2 turn-off depends on GATE1

turn-off and other conditions. Refer to the sectors cover-

ing high stress staged start mode and low stress staged

start mode for details.

Overcurrent Protection

The LTC4284 features two levels of protection from

short-circuit and overcurrent conditions. Load current is

monitored by SENSE1,2+ and SENSE1,2− pins and sense

resistors. There are two distinct thresholds for the sense

voltages: VILIM and VILIM(FAST). VILIM is configurable from

15mV to 30mV in 1mV steps and VILIM(FAST) is always

twice VILIM. See Current Limit Adjustment for details.

If the sense voltage of a channel reaches VILIM, the cor-

responding GATE is pulled down by 25mA current until

the associated active current limit loop is engaged. In

the event of a catastrophic short-circuit or a sudden

input step, where the sense voltage of a channel reaches

VILIM(FAST), the corresponding GATE is immediately pulled

down by a 1.2A current to limit peak current through the

MOSFET. When the sense voltage drops to VILIM, the

active current limit loop is engaged.

SOA Timer

During active current limit, the power dissipation in the

MOSFET is large. If this power dissipation persists, the

MOSFET can reach temperatures that cause damage.

MOSFET manufacturers specify the safe limits on operat-

ing voltage, current and time as a curve referred to as the

Safe Operating Area (SOA). Commonly, a circuit breaker

timer sets a maximum time for the MOSFET to operate in a

current limit mode. When this timer expires, the MOSFET

LTC4261 Datasheet(PDF) 24 Page - Analog Devices

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