LTC4261 datasheet(13/82 Pages) AD

13 / 82 page

LTC4284

Rev. B

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PIN FUNCTIONS

DRNS (Pin 21): Attenuated Drain Sense Input. Connect to

the tap of an external resistive divider between the drain

terminal of the N-channel MOSFET and VEE to monitor

the drain voltage. DRNS coupled with RTNS monitors the

output voltage for the load, which controls dV/dt inrush

current and current limit foldback. DRNS operates from

0 to 2.8V. Connect to VEE if unused.

EN# (Pin 1): Device Enable Input. Pull low to enable the

GATE outputs to turn-on after a startup debounce delay.

When pulled high, both GATE1 and GATE2 are turned

off. A high-to-low transition clears faults. Transitions are

recorded. Requires external pull-up. Debouncing with an

external capacitor is recommended when used to monitor

board present. Connect to VEE if unused.

Exposed Pad (Pin 45): Exposed Pad may be left open or

connected to device ground (VEE).

GATE1, GATE2 (Pin 18, Pin 19): N-Channel MOSFET Gate

Drive Outputs. The GATEs can be configured into single

driver, parallel, high stress staged start, and low stress

staged start modes. See Table 1 in Application Information

for details. The GATEs are pulled high by internal current

sources (>40μA) when VIN and INTVCC cross the UVLO

thresholds, UV and OV conditions are satisfied, no other

faults are present and the debounce delay expires. The

GATE1 and GATE2 voltages higher than VIN – 1.8V satisfy

one of the conditions to assert power good outputs. Upon

a low impedance output short, a 1.2A fast pull-down cur-

rent is immediately activated.

INTVCC (Pin 42): 5V Internal Supply Output. The output of

the internal linear regulator sources up to 30mA with an

UVLO threshold of 4V. The supply powers the data con-

verters, logic control circuitry, I2C interface and EEPROM.

Bypass with 1μF capacitor to VEE. INTVCC is not current

limited. When driving INTVCC with an external supply, VIN

and VZ must be left open or connected to INTVCC.

MODE (Pin 40): GATE Drive Mode Configuration Input.

Its voltage decodes four operation modes of GATE1 and

GATE2. Leaving MODE open enables the single driver

mode (Mode 1): GATE1 and GATE2 drive a single chan-

nel of MOSFETs. Connecting MODE to VEE enables the

parallel mode (Mode 2): GATE1 and GATE2 drive two par-

allel channels of MOSFETs that turn on simultaneously to

share the load current and turn off simultaneously upon

overload. Connecting MODE to VIN enables the high stress

staged start mode (Mode 3): GATE1 drives a high SOA

MOSFET that turns on first for startup and withstands the

stress under overload conditions, while GATE2 drives a

low RDS(ON) MOSFET as a bypass switch that turns on

after GATE1 is fully enhanced and turns off whenever

overload occurs. Connecting MODE to INTVCC enables

the low stress staged start mode (Mode 4): the turn-on

behavior of GATE1 and GATE2 is the same as Mode 3,

but GATE1 drives a low SOA trickle MOSFET and the low

RDS(ON) bypass MOSFET driven by GATE2 stays on under

overload to share the stress. See Applications Information

for more details.

OV (Pin 4): Overvoltage Detection Input. Connect to an

external resistive divider from VEE. When OV is above its

threshold of 1.406V, the GATE outputs pull low to turn off

the MOSFETs and an overvoltage fault is recorded. The

overvoltage fault does not affect the status of the power

good outputs. Connect to VEE if unused.

PGIO1, PGIO2 (Pin 29, Pin 30): General Purpose

Inputs/Outputs. Configurable to sequenced, inverted

and non-inverted power good outputs, general purpose

logic inputs and open-drain outputs. See Table 12 in

Application Information for details. If the PGIO2_ACLB

bit in CONTROL_1 register 0x0A is set, PGIO2 is config-

ured as inverted current limit engagement indicator after

startup. Connect to VEE if unused.

PGIO3 (Pin 31): General Purpose Input/Output.

Configurable to inverted and non-inverted power good

watchdog input (PGI# and PGI), general purpose logic

input and open-drain output. See Table 12 in Application

Information for details. Connect to VEE if unused.

PGIO4 (Pin 32): General Purpose Input/Output.

Configurable to inverted and non-inverted external fault

input (EXT_FAULTIN# and EXT_FAULTIN), general pur-

pose logic input and open-drain output. See Table 12 in

Application Information for details. Connect to INTVCC

through a 10kΩ pull-up resistor if unused.

LTC4261 Datasheet(PDF) 13 Page - Analog Devices

LTC4261 Datasheet(HTML) 13 Page - Analog Devices

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