LTC4282 datasheet(14/32 Pages) AD

14 / 32 page

LTC4238

Rev. 0

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limiting function of an RC network, but an RC network

may be used in low stress staged start to improve the

undershoot recovery time of the bypass MOSFET(s).

Current Limit Stability

For many applications the LTC4238 current limit loop is

stable without additional components. However, there are

certain conditions where additional components may be

needed to improve stability. The dominant pole of the

current limit circuit is set by the capacitance at the gate of

the external MOSFET, and larger gate capacitance makes

the current limit loop more stable. Usually a total of 10nF

GATE-to-SOURCE capacitance is sufficient for stability

and is provided by inherent MOSFET CGS. The stability of

the loop is degraded by reducing the size of the resistor

on a gate RC network if one is used, which may neces-

sitate additional GATE-to-SOURCE capacitance. The worst

case for current limit stability occurs when the output is

shorted to ground after a normal start-up. Board level

short-circuit testing is highly recommended as board lay-

out can also affect transient performance.

Parasitic MOSFET Oscillations

Not all circuit oscillations can be ascribed to the cur-

rent limit loop. Some higher frequency oscillations can

arise from the MOSFETs themselves. (See Rarely Asked

Questions 151, High-Side Current Sensing). There are two

possible parasitic oscillation mechanisms. The first type

of oscillation occurs at high frequencies, typically above

1MHz. This high frequency oscillation is easily damped

with gate resistors RG1 – RG4 as shown in Figure 1. In

some applications, one may find that these resistors

help in short-circuit transient recovery as well. However,

too large of a resistor will slow down the turn-off time.

The recommended RG1 – RG4 range is between 5Ω and

500Ω. 10Ω provides stability without affecting turn-off

time. These resistors must be located next to the MOSFET

gate pin with no other connections between them.

A second type of parasitic oscillation occurs at frequen-

cies between 200kHz and 800kHz when the MOSFET

source is loaded with less than 10μF, and the drain is

fed with an inductive impedance such as contributed by

wiring inductance. To prevent this second type of oscilla-

tion, load the source with more than 10μF and bypass the

input supply with a series 10Ω, 100nF snubber to ground.

Overcurrent Fault with a Basic Current Limit Timer

During active current limit, the power dissipation in the

MOSFET is large. If this power dissipation persists, the

MOSFET can reach temperatures that cause damage. A

basic current limit timer has a single capacitor connected

between TMR pin and GND and sets a maximum time for

the MOSFET to operate in a current limit mode. When

this timer expires, an over current fault is generated and

the MOSFET is turned off to protect it from overheating.

Current limiting begins when the current sense voltage

between the SENSE+ and SENSE– pins reaches the current

limit threshold level (which depends on foldback and the

voltage of the ISET pin). The corresponding GATE pin is

then pulled down and regulated to limit the current sense

voltage to the current limit value. In parallel mode, if either

GATE is in current limit during start-up then the current

limit timer starts to run. The external timer capacitor at

the TMR pin will be charged with a 20µA pull-up current.

After start-up, only when both GATE pins are regulated in

current limit will the current limit timer start to run. If at

least one of the GATE pins stops limiting current before

the TMR pin reaches the 2.56V threshold, then the TMR

pin will discharge with 5μA. For HSSS, LSSS or Single

Driver Modes, if the current sense voltage between the

SENSE1+ and SENSE1– pins reaches the current limit

threshold level, then the current limit timer will start to

run. For a given current limit time delay, tACL, use Equation

1 for setting the timing capacitor’s value:

CTMR = tACL • 8[nF/ms]

(1)

When the TMR pin reaches its 2.56V threshold, the

LTC4238 turns off both GATEs and generates an over-

current fault. The MOSFETs are turned off with a 10mA

current from GATE to SOURCE and a 1mA current from

GATE to ground. Open-drain output FLT# also pulls low.

After the fault, the TMR pin begins discharging with a 5μA

pull-down current. When the TMR pin reaches its 200mV

low threshold, it will cycle up with 20μA and down with

5μA 256 times to give the MOSFETs time to cool.

APPLICATIONS INFORMATION

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