LTC4282 datasheet(20/32 Pages) AD

20 / 32 page

LTC4238

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Figure 5. High Stress Staged Start Application

(a) 48V,60A Application Circuit with TA = 65°C

(b) Normal Start-Up Waveform

0.2m

PSMN3R7-100BSE

(OPTIONAL)

RG1

M2A

IPT015N10N5

RG2

360k

93.1k

3.01k

4.22k

0.1µF

CFET

0.33µF

62k

5.23k

CE1

2.7nF

CE2

22nF

RE3

1.13M

RTOP

59k

RBOTTOM

44.2k

0.1µF

M2B

IPT015N10N5

RG4

RG3

59k

CGATE

22nF

FLT#

TMR

VDD

CONFIG1

SENSE1–

SENSE1+

GATE1

SENSE2–

GATE2

SOURCE VDSFB

COMM

LTC4238

SENSE2+

ISET

CONFIG2

INTVCC

TMRFET

GND

48V

GND

BACKPLANE PLUG-IN

BOARD

SMC5K60A

×4

RS1

CE3

270nF

4238 F05a

RE1

4.75k, 1%

RE2

60k, 1%

VOUT

48V

60A

such a system without significant input voltage steps,

the worst-case operating condition for the MOSFET SOA

occurs when charging the load capacitance during start-

up. By limiting the start-up inrush current to a very low

level, the SOA demand for the start-up MOSFET is greatly

alleviated. Additionally, the bypass path which turns on

after start-up only needs inexpensive, switching regulator

class MOSFETs. Therefore, this architecture minimizes

5ms/DIV

4238 F05b

∆VGATE1

10V/DIV

∆VGATE2

10V/DIV

IINRUSH

5A/DIV

5V/DIV

5ms/DIV

4238 F05c

∆VGATE1

10V/DIV

∆VGATE2

10V/DIV

ISTARTUP

20A/DIV

TMR

2V/DIV

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