LTC4282 datasheet(26/32 Pages) AD

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LTC4238

Rev. 0

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VDS,MAX =

ICH(MAX) •RDS(ON),MAX

20A •3.7m

= 37mV

(11)

There is enough margin with the full current load for

VDD – SOURCE before reaching FET bad threshold of

100mV.

Since PSMN3R7-100BSE has about 10nF of gate

capacitance it is likely to be stable, but the short-circuit

stability of the current limit loop should be checked and

improved by adding capacitors from GATE to SOURCE

if needed.

Step 3. Select the RC network for the SOA timer following

the procedure as shown in the SOA Timer section. Three

thermal capacitors and three thermal resistors provide

fairly good curve fitting for the thermal impedance plot

of the chosen MOSFET, PSMN3R7-100BSE in the range

between 100μs and 100ms (wide enough for typical oper-

ating conditions of this application): Cθ1 = 0.001J/°C,

Rθ1 = 0.013°C/W, Cθ2 = 0.008J/°C, Rθ2 = 0.16°C/W,

Cθ3 = 0.1J/°C, Rθ3 = 0.27°C/W. The conversion constant

is given by:

VDS,MAX •ID,MAX

ITMR(UP),MAX

•

VTMR(TH)

∆TMAX

58V •20mV

400µA •0.5m

•

2.56V

175

°C–65°C

= 1.4•105

°C

⎡

⎣

⎢

⎤

⎦

⎥

(12)

where ΔTMAX is the maximum allowable temperature

rise and chosen to be 110°C, which corresponds to a

maximum MOSFET temperature of 175°C at an operat-

ing temperature of 65°C. The thermal R and C values are

then converted to electric R and C values as shown in

the SOA timer section. After the electrical R and C val-

ues are computed, choose the closest next-larger avail-

able resistor value and the closest next-smaller available

capacitor value. Then the resistance corresponding to the

thermal resistance of the board is added to the termi-

nation resistance (the largest one). Assuming a 5°C/W

board thermal resistance in this application, it is con-

verted to 5 • 1.4 • 105 = 700k. If the computed resistance

for the board thermal resistance is over 1M, choose 1M.

This avoids accuracy degradation due to board leakage

currents. The resulting electrical capacitors and resis-

tors are CE1 = 6.8nF, RE1 = 1.82k, CE2 = 56nF, RE2 =

22.6k, CE3 = 680nF, RE3 = 750k, as shown in Figure 1 and

Figure 3. After the SOA timer is configured, run simula-

tions in LTspice to ensure TMR does not reach its 2.56V

trip point in any operating conditions including start-up

and input step. When it trips in fault conditions such as

output overload or short-circuit, verify the peak tempera-

ture of the MOSFET matches the proposed maximum

temperature. Iterations of the above procedure may be

needed before the RC network is finalized.

Step 4. Design the FET-bad timer. During start-up the FET-

Bad Timer is running. The load capacitor must be fully

charged before this timer expires, or the gate outputs will

be turned off once a FET-bad fault is triggered. For a start-

up time of 3.6ms and taking into account the tolerance of

components, we choose having a 2× safety margin.

CFET = 2 •

TSTART-UP

128ms / µF

= 2 •

3.6ms

128ms / µF

≈ 56nF

(13)

The closest larger available capacitance 62nF is picked.

Step 5. VUV(ON) = 36V, VUV(OFF) = 60V, VPWRGD(UP) =

33V. Select resistive dividers for UV/OV and Power Good

inputs. The UV and OV resistor string values can be solved

in the following method. To keep the error due to 1μA of

leakage to less than 1% choose a divider current of at

least 200μA. R1 < 2.56V/200μA = 12.8kΩ. Then calculate:

VOV(OFF)

VUV(ON)

•R1•

UVTH(RISING)

OVTH(FALLING)

– R1

(14)

VUV(ON) •(R1+ R2)

UVTH(RISING)

– R1– R2

(15)

In our case we choose R1 to be 4.22k to give a resis-

tor string current greater than 200μA. Then, solving the

equations results in R2 = 3.01k and R3 = 93.1k. A 0.1μF

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